Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
376582 |
1 |
|
|
T2 |
2 |
|
T3 |
60 |
|
T39 |
2 |
auto[1] |
315342 |
1 |
|
|
T2 |
778 |
|
T39 |
746 |
|
T40 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173027 |
1 |
|
|
T2 |
192 |
|
T3 |
16 |
|
T39 |
184 |
lower_val |
171521 |
1 |
|
|
T2 |
182 |
|
T3 |
16 |
|
T39 |
187 |
zero_val |
1685 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T39 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
267292 |
1 |
|
|
T2 |
222 |
|
T3 |
28 |
|
T39 |
200 |
lower_val |
266354 |
1 |
|
|
T2 |
204 |
|
T3 |
32 |
|
T39 |
172 |
zero_val |
158278 |
1 |
|
|
T2 |
354 |
|
T39 |
376 |
|
T40 |
306 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47071 |
1 |
|
|
T3 |
6 |
|
T38 |
4 |
|
T41 |
93 |
higher_val |
higher_val |
auto[1] |
19883 |
1 |
|
|
T2 |
53 |
|
T39 |
55 |
|
T40 |
50 |
higher_val |
lower_val |
auto[0] |
47146 |
1 |
|
|
T3 |
10 |
|
T38 |
6 |
|
T41 |
98 |
higher_val |
lower_val |
auto[1] |
19435 |
1 |
|
|
T2 |
57 |
|
T39 |
46 |
|
T40 |
32 |
higher_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T13 |
1 |
higher_val |
zero_val |
auto[1] |
39400 |
1 |
|
|
T2 |
82 |
|
T39 |
83 |
|
T40 |
85 |
lower_val |
higher_val |
auto[0] |
46435 |
1 |
|
|
T3 |
7 |
|
T38 |
2 |
|
T40 |
1 |
lower_val |
higher_val |
auto[1] |
19662 |
1 |
|
|
T2 |
55 |
|
T39 |
53 |
|
T40 |
42 |
lower_val |
lower_val |
auto[0] |
46537 |
1 |
|
|
T3 |
9 |
|
T39 |
1 |
|
T41 |
94 |
lower_val |
lower_val |
auto[1] |
19472 |
1 |
|
|
T2 |
52 |
|
T39 |
43 |
|
T40 |
36 |
lower_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T203 |
1 |
lower_val |
zero_val |
auto[1] |
39330 |
1 |
|
|
T2 |
74 |
|
T39 |
90 |
|
T40 |
55 |
zero_val |
higher_val |
auto[0] |
511 |
1 |
|
|
T40 |
1 |
|
T41 |
1 |
|
T67 |
1 |
zero_val |
higher_val |
auto[1] |
112 |
1 |
|
|
T2 |
1 |
|
T96 |
1 |
|
T113 |
1 |
zero_val |
lower_val |
auto[0] |
556 |
1 |
|
|
T3 |
1 |
|
T39 |
1 |
|
T38 |
1 |
zero_val |
lower_val |
auto[1] |
107 |
1 |
|
|
T39 |
1 |
|
T113 |
1 |
|
T4 |
2 |
zero_val |
zero_val |
auto[0] |
237 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T45 |
1 |
zero_val |
zero_val |
auto[1] |
162 |
1 |
|
|
T2 |
1 |
|
T39 |
1 |
|
T96 |
1 |