Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10354	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9006	1			T2	17		T3	5		T39	19
len_5001_7500	14511	1			T2	17		T3	11		T39	18
len_2501_5000	9295	1			T2	17		T3	2		T39	18
len_1025_2500	5401	1			T2	10		T3	4		T39	11
len_769_1024	6158	1			T2	2		T39	2		T40	2
len_513_768	6531	1			T2	2		T39	2		T40	3
len_257_512	21017	1			T2	2		T3	1		T39	2
len_0_256	257048	1			T2	290		T3	7		T39	274
len_keccak_block_sizes[72]	727	1			T2	2		T39	2		T40	2
len_keccak_block_sizes[104]	627	1			T2	2		T39	2		T40	2
len_keccak_block_sizes[136]	521	1			T2	2		T39	2		T41	2
len_keccak_block_sizes[144]	428	1			T2	2		T69	3		T66	3
len_keccak_block_sizes[168]	322	1			T69	3		T66	3		T96	3
len_1	748	1			T2	2		T39	2		T40	2
len_0	1128	1			T2	2		T39	2		T40	2