Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99721248	1			T2	222065		T3	382		T39	206031
all_pins[1]	99721248	1			T2	222065		T3	382		T39	206031
all_pins[2]	99721248	1			T2	222065		T3	382		T39	206031

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298383950	1			T2	665605		T3	1099		T39	617524
values[0x1]	779794	1			T2	590		T3	47		T39	569
transitions[0x0=>0x1]	777949	1			T2	590		T3	47		T39	569
transitions[0x1=>0x0]	777982	1			T2	590		T3	47		T39	569

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99213973	1			T2	221475		T3	337		T39	205462
all_pins[0]	values[0x1]	507275	1			T2	590		T3	45		T39	569
all_pins[0]	transitions[0x0=>0x1]	507262	1			T2	590		T3	45		T39	569
all_pins[0]	transitions[0x1=>0x0]	5524	1			T3	2		T26	72		T17	2
all_pins[1]	values[0x0]	99715711	1			T2	222065		T3	380		T39	206031
all_pins[1]	values[0x1]	5537	1			T3	2		T26	72		T17	2
all_pins[1]	transitions[0x0=>0x1]	5321	1			T3	2		T26	72		T17	2
all_pins[1]	transitions[0x1=>0x0]	266766	1			T27	263		T4	1676		T5	6908
all_pins[2]	values[0x0]	99454266	1			T2	222065		T3	382		T39	206031
all_pins[2]	values[0x1]	266982	1			T27	263		T4	1676		T5	6908
all_pins[2]	transitions[0x0=>0x1]	265366	1			T27	263		T4	1667		T5	6859
all_pins[2]	transitions[0x1=>0x0]	505692	1			T2	590		T3	45		T39	569