Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10643821 |
1 |
|
|
T2 |
2730 |
|
T3 |
4746 |
|
T39 |
2992 |
auto[1] |
10643721 |
1 |
|
|
T2 |
2730 |
|
T3 |
4746 |
|
T39 |
2992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21049888 |
1 |
|
|
T2 |
5460 |
|
T3 |
9446 |
|
T39 |
5984 |
triple_byte_access |
78924 |
1 |
|
|
T3 |
18 |
|
T26 |
54 |
|
T69 |
558 |
halfword_access |
79434 |
1 |
|
|
T3 |
16 |
|
T26 |
48 |
|
T69 |
558 |
byte_access |
79296 |
1 |
|
|
T3 |
12 |
|
T26 |
66 |
|
T69 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10524994 |
1 |
|
|
T2 |
2730 |
|
T3 |
4723 |
|
T39 |
2992 |
auto[0] |
triple_byte_access |
39462 |
1 |
|
|
T3 |
9 |
|
T26 |
27 |
|
T69 |
279 |
auto[0] |
halfword_access |
39717 |
1 |
|
|
T3 |
8 |
|
T26 |
24 |
|
T69 |
279 |
auto[0] |
byte_access |
39648 |
1 |
|
|
T3 |
6 |
|
T26 |
33 |
|
T69 |
279 |
auto[1] |
word_access |
10524894 |
1 |
|
|
T2 |
2730 |
|
T3 |
4723 |
|
T39 |
2992 |
auto[1] |
triple_byte_access |
39462 |
1 |
|
|
T3 |
9 |
|
T26 |
27 |
|
T69 |
279 |
auto[1] |
halfword_access |
39717 |
1 |
|
|
T3 |
8 |
|
T26 |
24 |
|
T69 |
279 |
auto[1] |
byte_access |
39648 |
1 |
|
|
T3 |
6 |
|
T26 |
33 |
|
T69 |
279 |