Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98471568	1			T3	455135		T6	20852		T7	22124
all_values[1]	98471568	1			T3	455135		T6	20852		T7	22124
all_values[2]	98471568	1			T3	455135		T6	20852		T7	22124

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

485252

1

T3

21

T6

213

T7

416

auto[1]

294929452

1

T3

136538

T6

62343

T7

65956

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293903781

1

T3

135523

T6

61926

T7

65715

auto[1]

1510923

1

T3

10167

T6

630

T7

657

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	155193	1			T3	1		T7	410		T11	254
all_values[0]	auto[0]	auto[1]	1836	1			T3	2		T7	6		T11	4
all_values[0]	auto[1]	auto[0]	97812734	1			T3	451745		T6	20642		T7	21495
all_values[0]	auto[1]	auto[1]	501805	1			T3	3387		T6	210		T7	213
all_values[1]	auto[0]	auto[0]	150649	1			T3	4		T6	212		T11	274
all_values[1]	auto[0]	auto[1]	1526	1			T3	3		T6	1		T11	5
all_values[1]	auto[1]	auto[0]	97817278	1			T3	451742		T6	20430		T7	21905
all_values[1]	auto[1]	auto[1]	502115	1			T3	3386		T6	209		T7	219
all_values[2]	auto[0]	auto[0]	174593	1			T3	6		T11	232		T36	69
all_values[2]	auto[0]	auto[1]	1455	1			T3	5		T11	2		T36	9
all_values[2]	auto[1]	auto[0]	97793334	1			T3	451740		T6	20642		T7	21905
all_values[2]	auto[1]	auto[1]	502186	1			T3	3384		T6	210		T7	219