Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
396440 |
1 |
|
|
T1 |
2 |
|
T3 |
4530 |
|
T6 |
2 |
auto[1] |
287430 |
1 |
|
|
T6 |
340 |
|
T7 |
286 |
|
T37 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171746 |
1 |
|
|
T3 |
1176 |
|
T6 |
87 |
|
T7 |
70 |
lower_val |
169179 |
1 |
|
|
T3 |
1024 |
|
T6 |
94 |
|
T7 |
80 |
zero_val |
1699 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
271018 |
1 |
|
|
T3 |
2238 |
|
T6 |
86 |
|
T7 |
74 |
lower_val |
269126 |
1 |
|
|
T1 |
2 |
|
T3 |
2292 |
|
T6 |
84 |
zero_val |
143726 |
1 |
|
|
T6 |
172 |
|
T7 |
146 |
|
T37 |
338 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
50024 |
1 |
|
|
T3 |
559 |
|
T11 |
48 |
|
T36 |
9 |
higher_val |
higher_val |
auto[1] |
17981 |
1 |
|
|
T6 |
20 |
|
T7 |
21 |
|
T37 |
40 |
higher_val |
lower_val |
auto[0] |
49560 |
1 |
|
|
T3 |
617 |
|
T11 |
26 |
|
T36 |
9 |
higher_val |
lower_val |
auto[1] |
18074 |
1 |
|
|
T6 |
28 |
|
T7 |
17 |
|
T37 |
46 |
higher_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T7 |
1 |
|
T22 |
2 |
|
T107 |
1 |
higher_val |
zero_val |
auto[1] |
36031 |
1 |
|
|
T6 |
39 |
|
T7 |
31 |
|
T37 |
93 |
lower_val |
higher_val |
auto[0] |
49325 |
1 |
|
|
T3 |
511 |
|
T11 |
34 |
|
T36 |
8 |
lower_val |
higher_val |
auto[1] |
17900 |
1 |
|
|
T6 |
26 |
|
T7 |
18 |
|
T37 |
28 |
lower_val |
lower_val |
auto[0] |
48814 |
1 |
|
|
T3 |
513 |
|
T11 |
32 |
|
T36 |
9 |
lower_val |
lower_val |
auto[1] |
17732 |
1 |
|
|
T6 |
23 |
|
T7 |
22 |
|
T37 |
37 |
lower_val |
zero_val |
auto[0] |
65 |
1 |
|
|
T22 |
1 |
|
T182 |
1 |
|
T107 |
1 |
lower_val |
zero_val |
auto[1] |
35343 |
1 |
|
|
T6 |
45 |
|
T7 |
40 |
|
T37 |
89 |
zero_val |
higher_val |
auto[0] |
543 |
1 |
|
|
T3 |
1 |
|
T11 |
1 |
|
T36 |
1 |
zero_val |
higher_val |
auto[1] |
86 |
1 |
|
|
T5 |
2 |
|
T183 |
1 |
|
T22 |
2 |
zero_val |
lower_val |
auto[0] |
527 |
1 |
|
|
T1 |
1 |
|
T38 |
1 |
|
T39 |
1 |
zero_val |
lower_val |
auto[1] |
109 |
1 |
|
|
T183 |
1 |
|
T22 |
2 |
|
T184 |
1 |
zero_val |
zero_val |
auto[0] |
246 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[1] |
188 |
1 |
|
|
T5 |
1 |
|
T22 |
2 |
|
T184 |
1 |