Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10292	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8711	1			T3	38		T36	5		T37	24
len_5001_7500	13714	1			T3	36		T36	18		T37	24
len_2501_5000	9043	1			T3	36		T36	3		T37	24
len_1025_2500	5262	1			T3	22		T36	2		T37	14
len_769_1024	5890	1			T3	4		T6	33		T7	34
len_513_768	6354	1			T3	4		T6	35		T7	41
len_257_512	20869	1			T3	52		T6	39		T7	33
len_0_256	255399	1			T3	2017		T6	29		T7	36
len_keccak_block_sizes[72]	715	1			T3	3		T11	1		T37	2
len_keccak_block_sizes[104]	613	1			T3	3		T37	2		T91	2
len_keccak_block_sizes[136]	517	1			T3	3		T185	2		T186	2
len_keccak_block_sizes[144]	414	1			T3	3		T11	1		T185	2
len_keccak_block_sizes[168]	319	1			T3	3		T184	3		T187	3
len_1	754	1			T3	3		T37	2		T39	2
len_0	1179	1			T3	3		T37	2		T39	2