Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98471568	1			T3	455135		T6	20852		T7	22124
all_pins[1]	98471568	1			T3	455135		T6	20852		T7	22124
all_pins[2]	98471568	1			T3	455135		T6	20852		T7	22124

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	294640180	1			T3	136201		T6	62297		T7	66158
values[0x1]	774524	1			T3	3387		T6	259		T7	214
transitions[0x0=>0x1]	772688	1			T3	3387		T6	259		T7	214
transitions[0x1=>0x0]	772711	1			T3	3387		T6	259		T7	214

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97969763	1			T3	451748		T6	20642		T7	21911
all_pins[0]	values[0x1]	501805	1			T3	3387		T6	210		T7	213
all_pins[0]	transitions[0x0=>0x1]	501792	1			T3	3387		T6	210		T7	213
all_pins[0]	transitions[0x1=>0x0]	5653	1			T6	49		T7	1		T25	2
all_pins[1]	values[0x0]	98465902	1			T3	455135		T6	20803		T7	22123
all_pins[1]	values[0x1]	5666	1			T6	49		T7	1		T25	2
all_pins[1]	transitions[0x0=>0x1]	5413	1			T6	49		T7	1		T25	2
all_pins[1]	transitions[0x1=>0x0]	266800	1			T11	1262		T38	423		T26	1564
all_pins[2]	values[0x0]	98204515	1			T3	455135		T6	20852		T7	22124
all_pins[2]	values[0x1]	267053	1			T11	1262		T38	423		T26	1564
all_pins[2]	transitions[0x0=>0x1]	265483	1			T11	1262		T38	422		T26	1564
all_pins[2]	transitions[0x1=>0x0]	500258	1			T3	3387		T6	210		T7	213