Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	614	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5131	1			T6	16		T7	29		T11	20
len_601_800	11568	1			T6	54		T7	44		T11	40
len_401_600	7724	1			T6	34		T7	32		T11	25
len_201_400	16126	1			T3	251		T6	17		T7	22
len_65_200	73386	1			T3	680		T6	7		T7	10
len_min_for_xof_require_squeeze	1007	1			T3	10		T6	1		T7	1
len_keccak_block_sizes[72]	759	1			T3	5		T36	1		T76	1
len_keccak_block_sizes[104]	750	1			T3	5		T36	1		T76	1
len_keccak_block_sizes[136]	753	1			T3	5		T76	1		T22	2
len_keccak_block_sizes[144]	282	1			T3	5		T184	5		T188	5
len_keccak_block_sizes[168]	282	1			T3	5		T184	5		T188	5
len_datapath_width	13694	1			T3	5		T6	1		T39	246
len_2_63	212061	1			T3	1329		T6	38		T7	5
len_1	35	1			T7	1		T76	2		T22	1