Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	96944775	1			T2	13945		T17	292		T6	10044
all_values[1]	96944775	1			T2	13945		T17	292		T6	10044
all_values[2]	96944775	1			T2	13945		T17	292		T6	10044

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523217

1

T2

198

T17

99

T19

1076

auto[1]

290311108

1

T2

41637

T17

777

T6

30132

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289342443

1

T2

41400

T17

825

T6

29841

auto[1]

1491882

1

T2

435

T17

51

T6

291

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	182920	1			T2	64		T17	89		T19	330
all_values[0]	auto[0]	auto[1]	2120	1			T2	2		T17	10		T19	2
all_values[0]	auto[1]	auto[0]	96264561	1			T2	13736		T17	186		T6	9947
all_values[0]	auto[1]	auto[1]	495174	1			T2	143		T17	7		T6	97
all_values[1]	auto[0]	auto[0]	157730	1			T2	64		T19	330		T44	3
all_values[1]	auto[0]	auto[1]	1514	1			T2	2		T19	2		T44	4
all_values[1]	auto[1]	auto[0]	96289751	1			T2	13736		T17	275		T6	9947
all_values[1]	auto[1]	auto[1]	495780	1			T2	143		T17	17		T6	97
all_values[2]	auto[0]	auto[0]	177447	1			T2	64		T19	409		T7	193
all_values[2]	auto[0]	auto[1]	1486	1			T2	2		T19	3		T7	3
all_values[2]	auto[1]	auto[0]	96270034	1			T2	13736		T17	275		T6	9947
all_values[2]	auto[1]	auto[1]	495808	1			T2	143		T17	17		T6	97