Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344420 |
1 |
|
|
T2 |
2 |
|
T17 |
18 |
|
T6 |
2 |
auto[1] |
332614 |
1 |
|
|
T2 |
290 |
|
T6 |
188 |
|
T19 |
276 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
169789 |
1 |
|
|
T2 |
58 |
|
T17 |
2 |
|
T6 |
41 |
lower_val |
167381 |
1 |
|
|
T2 |
82 |
|
T17 |
6 |
|
T6 |
44 |
zero_val |
1728 |
1 |
|
|
T2 |
1 |
|
T17 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254692 |
1 |
|
|
T2 |
56 |
|
T17 |
6 |
|
T6 |
42 |
lower_val |
256424 |
1 |
|
|
T2 |
82 |
|
T17 |
12 |
|
T6 |
58 |
zero_val |
165918 |
1 |
|
|
T2 |
154 |
|
T6 |
90 |
|
T19 |
148 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42708 |
1 |
|
|
T7 |
56 |
|
T35 |
45 |
|
T61 |
1 |
higher_val |
higher_val |
auto[1] |
21032 |
1 |
|
|
T2 |
15 |
|
T6 |
8 |
|
T19 |
21 |
higher_val |
lower_val |
auto[0] |
43310 |
1 |
|
|
T17 |
2 |
|
T7 |
45 |
|
T44 |
1 |
higher_val |
lower_val |
auto[1] |
20721 |
1 |
|
|
T2 |
13 |
|
T6 |
18 |
|
T19 |
20 |
higher_val |
zero_val |
auto[0] |
66 |
1 |
|
|
T14 |
1 |
|
T32 |
1 |
|
T185 |
1 |
higher_val |
zero_val |
auto[1] |
41952 |
1 |
|
|
T2 |
30 |
|
T6 |
15 |
|
T19 |
45 |
lower_val |
higher_val |
auto[0] |
42330 |
1 |
|
|
T17 |
3 |
|
T7 |
39 |
|
T35 |
52 |
lower_val |
higher_val |
auto[1] |
20492 |
1 |
|
|
T2 |
13 |
|
T6 |
10 |
|
T19 |
9 |
lower_val |
lower_val |
auto[0] |
43273 |
1 |
|
|
T17 |
3 |
|
T7 |
43 |
|
T35 |
41 |
lower_val |
lower_val |
auto[1] |
20653 |
1 |
|
|
T2 |
29 |
|
T6 |
9 |
|
T19 |
22 |
lower_val |
zero_val |
auto[0] |
63 |
1 |
|
|
T2 |
1 |
|
T64 |
1 |
|
T138 |
1 |
lower_val |
zero_val |
auto[1] |
40570 |
1 |
|
|
T2 |
39 |
|
T6 |
25 |
|
T19 |
27 |
zero_val |
higher_val |
auto[0] |
499 |
1 |
|
|
T38 |
1 |
|
T35 |
1 |
|
T32 |
1 |
zero_val |
higher_val |
auto[1] |
104 |
1 |
|
|
T19 |
1 |
|
T44 |
4 |
|
T32 |
1 |
zero_val |
lower_val |
auto[0] |
570 |
1 |
|
|
T17 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
124 |
1 |
|
|
T44 |
1 |
|
T32 |
1 |
|
T61 |
4 |
zero_val |
zero_val |
auto[0] |
256 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T34 |
1 |
zero_val |
zero_val |
auto[1] |
175 |
1 |
|
|
T19 |
1 |
|
T44 |
1 |
|
T32 |
1 |