Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	96944775	1			T2	13945		T17	292		T6	10044
all_pins[1]	96944775	1			T2	13945		T17	292		T6	10044
all_pins[2]	96944775	1			T2	13945		T17	292		T6	10044

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	290080417	1			T2	41692		T17	868		T6	30012
values[0x1]	753908	1			T2	143		T17	8		T6	120
transitions[0x0=>0x1]	752202	1			T2	143		T17	8		T6	120
transitions[0x1=>0x0]	752225	1			T2	143		T17	8		T6	120

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96449601	1			T2	13802		T17	285		T6	9947
all_pins[0]	values[0x1]	495174	1			T2	143		T17	7		T6	97
all_pins[0]	transitions[0x0=>0x1]	495158	1			T2	143		T17	7		T6	97
all_pins[0]	transitions[0x1=>0x0]	5801	1			T17	1		T6	23		T19	75
all_pins[1]	values[0x0]	96938958	1			T2	13945		T17	291		T6	10021
all_pins[1]	values[0x1]	5817	1			T17	1		T6	23		T19	75
all_pins[1]	transitions[0x0=>0x1]	5636	1			T17	1		T6	23		T19	75
all_pins[1]	transitions[0x1=>0x0]	252736	1			T14	8315		T15	7102		T20	1120
all_pins[2]	values[0x0]	96691858	1			T2	13945		T17	292		T6	10044
all_pins[2]	values[0x1]	252917	1			T14	8315		T15	7113		T20	1120
all_pins[2]	transitions[0x0=>0x1]	251408	1			T14	8259		T15	7066		T20	1120
all_pins[2]	transitions[0x1=>0x0]	493688	1			T2	143		T17	7		T6	97