Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	617	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5039	1			T2	19		T6	5		T19	22
len_601_800	11498	1			T2	43		T6	30		T19	53
len_401_600	7722	1			T2	20		T6	18		T19	26
len_201_400	16227	1			T2	6		T6	7		T19	11
len_65_200	72056	1			T2	5		T19	16		T7	9
len_min_for_xof_require_squeeze	978	1			T44	10		T35	1		T61	9
len_keccak_block_sizes[72]	735	1			T44	5		T35	1		T39	3
len_keccak_block_sizes[104]	731	1			T44	5		T39	2		T61	9
len_keccak_block_sizes[136]	732	1			T44	5		T35	1		T61	9
len_keccak_block_sizes[144]	277	1			T7	1		T44	5		T62	5
len_keccak_block_sizes[168]	277	1			T44	5		T62	5		T186	5
len_datapath_width	13912	1			T17	3		T19	1		T44	5
len_2_63	209642	1			T2	52		T17	6		T6	34
len_1	39	1			T35	2		T16	1		T187	1