Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332347 |
1 |
|
|
T2 |
176 |
|
T17 |
9 |
|
T6 |
112 |
auto[1] |
3315 |
1 |
|
|
T1 |
1 |
|
T2 |
21 |
|
T6 |
15 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
301033 |
1 |
|
|
T2 |
108 |
|
T6 |
67 |
|
T19 |
39 |
auto[1] |
34629 |
1 |
|
|
T1 |
1 |
|
T2 |
89 |
|
T17 |
9 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322230 |
1 |
|
|
T2 |
160 |
|
T17 |
9 |
|
T6 |
90 |
auto[1] |
13432 |
1 |
|
|
T1 |
1 |
|
T2 |
37 |
|
T6 |
37 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13432 |
1 |
|
|
T1 |
1 |
|
T2 |
37 |
|
T6 |
37 |
sw_kmac_invalid_sideload |
322230 |
1 |
|
|
T2 |
160 |
|
T17 |
9 |
|
T6 |
90 |
app_valid_sideload |
13432 |
1 |
|
|
T1 |
1 |
|
T2 |
37 |
|
T6 |
37 |
app_invalid_sideload |
322230 |
1 |
|
|
T2 |
160 |
|
T17 |
9 |
|
T6 |
90 |