Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10211039 |
1 |
|
|
T2 |
18276 |
|
T17 |
96 |
|
T6 |
11399 |
auto[1] |
10211039 |
1 |
|
|
T2 |
18276 |
|
T17 |
96 |
|
T6 |
11399 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20191750 |
1 |
|
|
T2 |
36398 |
|
T17 |
192 |
|
T6 |
22698 |
triple_byte_access |
76878 |
1 |
|
|
T2 |
58 |
|
T6 |
34 |
|
T19 |
60 |
halfword_access |
76776 |
1 |
|
|
T2 |
38 |
|
T6 |
32 |
|
T19 |
62 |
byte_access |
76674 |
1 |
|
|
T2 |
58 |
|
T6 |
34 |
|
T19 |
82 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10095875 |
1 |
|
|
T2 |
18199 |
|
T17 |
96 |
|
T6 |
11349 |
auto[0] |
triple_byte_access |
38439 |
1 |
|
|
T2 |
29 |
|
T6 |
17 |
|
T19 |
30 |
auto[0] |
halfword_access |
38388 |
1 |
|
|
T2 |
19 |
|
T6 |
16 |
|
T19 |
31 |
auto[0] |
byte_access |
38337 |
1 |
|
|
T2 |
29 |
|
T6 |
17 |
|
T19 |
41 |
auto[1] |
word_access |
10095875 |
1 |
|
|
T2 |
18199 |
|
T17 |
96 |
|
T6 |
11349 |
auto[1] |
triple_byte_access |
38439 |
1 |
|
|
T2 |
29 |
|
T6 |
17 |
|
T19 |
30 |
auto[1] |
halfword_access |
38388 |
1 |
|
|
T2 |
19 |
|
T6 |
16 |
|
T19 |
31 |
auto[1] |
byte_access |
38337 |
1 |
|
|
T2 |
29 |
|
T6 |
17 |
|
T19 |
41 |