Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99352776	1			T1	1103		T2	3167		T3	1106
all_values[1]	99352776	1			T1	1103		T2	3167		T3	1106
all_values[2]	99352776	1			T1	1103		T2	3167		T3	1106

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

481099

1

T1

57

T3

413

T34

3

auto[1]

297577229

1

T1

3252

T2

9501

T3

2905

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296549385

1

T1

3000

T2

8646

T3

3294

auto[1]

1508943

1

T1

309

T2

855

T3

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	163833	1			T1	49		T35	5		T8	198
all_values[0]	auto[0]	auto[1]	2001	1			T1	8		T35	6		T8	4
all_values[0]	auto[1]	auto[0]	98685962	1			T1	951		T2	2882		T3	1098
all_values[0]	auto[1]	auto[1]	500980	1			T1	95		T2	285		T3	8
all_values[1]	auto[0]	auto[0]	165398	1			T34	2		T35	1		T9	203
all_values[1]	auto[0]	auto[1]	1568	1			T34	1		T35	2		T9	2
all_values[1]	auto[1]	auto[0]	98684397	1			T1	1000		T2	2882		T3	1098
all_values[1]	auto[1]	auto[1]	501413	1			T1	103		T2	285		T3	8
all_values[2]	auto[0]	auto[0]	146726	1			T3	411		T7	134		T35	1
all_values[2]	auto[0]	auto[1]	1573	1			T3	2		T7	1		T35	2
all_values[2]	auto[1]	auto[0]	98703069	1			T1	1000		T2	2882		T3	687
all_values[2]	auto[1]	auto[1]	501408	1			T1	103		T2	285		T3	6