Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370954 |
1 |
|
|
T1 |
130 |
|
T2 |
2 |
|
T3 |
12 |
auto[1] |
313828 |
1 |
|
|
T2 |
366 |
|
T35 |
746 |
|
T8 |
264 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171554 |
1 |
|
|
T1 |
36 |
|
T2 |
98 |
|
T34 |
1128 |
lower_val |
170148 |
1 |
|
|
T1 |
26 |
|
T2 |
94 |
|
T3 |
8 |
zero_val |
1768 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
265532 |
1 |
|
|
T1 |
62 |
|
T2 |
96 |
|
T3 |
6 |
lower_val |
262466 |
1 |
|
|
T1 |
68 |
|
T2 |
86 |
|
T3 |
6 |
zero_val |
156784 |
1 |
|
|
T2 |
186 |
|
T35 |
348 |
|
T8 |
124 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46696 |
1 |
|
|
T1 |
15 |
|
T34 |
587 |
|
T7 |
27 |
higher_val |
higher_val |
auto[1] |
19838 |
1 |
|
|
T2 |
27 |
|
T35 |
49 |
|
T8 |
19 |
higher_val |
lower_val |
auto[0] |
45896 |
1 |
|
|
T1 |
21 |
|
T2 |
1 |
|
T34 |
541 |
higher_val |
lower_val |
auto[1] |
19760 |
1 |
|
|
T2 |
26 |
|
T35 |
46 |
|
T8 |
21 |
higher_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T35 |
1 |
|
T37 |
1 |
|
T71 |
1 |
higher_val |
zero_val |
auto[1] |
39286 |
1 |
|
|
T2 |
44 |
|
T35 |
89 |
|
T8 |
32 |
lower_val |
higher_val |
auto[0] |
46294 |
1 |
|
|
T1 |
12 |
|
T3 |
4 |
|
T34 |
611 |
lower_val |
higher_val |
auto[1] |
19452 |
1 |
|
|
T2 |
24 |
|
T35 |
55 |
|
T8 |
12 |
lower_val |
lower_val |
auto[0] |
45709 |
1 |
|
|
T1 |
14 |
|
T3 |
4 |
|
T34 |
537 |
lower_val |
lower_val |
auto[1] |
19592 |
1 |
|
|
T2 |
19 |
|
T35 |
47 |
|
T8 |
20 |
lower_val |
zero_val |
auto[0] |
98 |
1 |
|
|
T9 |
1 |
|
T37 |
1 |
|
T199 |
1 |
lower_val |
zero_val |
auto[1] |
39003 |
1 |
|
|
T2 |
51 |
|
T35 |
82 |
|
T8 |
40 |
zero_val |
higher_val |
auto[0] |
528 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T34 |
3 |
zero_val |
higher_val |
auto[1] |
120 |
1 |
|
|
T39 |
1 |
|
T74 |
2 |
|
T200 |
2 |
zero_val |
lower_val |
auto[0] |
548 |
1 |
|
|
T2 |
1 |
|
T34 |
4 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
130 |
1 |
|
|
T71 |
1 |
|
T200 |
1 |
|
T48 |
1 |
zero_val |
zero_val |
auto[0] |
262 |
1 |
|
|
T35 |
1 |
|
T9 |
1 |
|
T39 |
1 |
zero_val |
zero_val |
auto[1] |
180 |
1 |
|
|
T35 |
2 |
|
T39 |
1 |
|
T71 |
3 |