Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99352776	1			T1	1103		T2	3167		T3	1106
all_pins[1]	99352776	1			T1	1103		T2	3167		T3	1106
all_pins[2]	99352776	1			T1	1103		T2	3167		T3	1106

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297252356	1			T1	3214		T2	9211		T3	3310
values[0x1]	805972	1			T1	95		T2	290		T3	8
transitions[0x0=>0x1]	803863	1			T1	95		T2	290		T3	8
transitions[0x1=>0x0]	803890	1			T1	95		T2	290		T3	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98851796	1			T1	1008		T2	2882		T3	1098
all_pins[0]	values[0x1]	500980	1			T1	95		T2	285		T3	8
all_pins[0]	transitions[0x0=>0x1]	500963	1			T1	95		T2	285		T3	8
all_pins[0]	transitions[0x1=>0x0]	6428	1			T2	5		T7	58		T8	38
all_pins[1]	values[0x0]	99346331	1			T1	1103		T2	3162		T3	1106
all_pins[1]	values[0x1]	6445	1			T2	5		T7	58		T8	38
all_pins[1]	transitions[0x0=>0x1]	6178	1			T2	5		T7	58		T8	38
all_pins[1]	transitions[0x1=>0x0]	298280	1			T7	189		T16	4573		T22	23
all_pins[2]	values[0x0]	99054229	1			T1	1103		T2	3167		T3	1106
all_pins[2]	values[0x1]	298547	1			T7	189		T16	4581		T22	23
all_pins[2]	transitions[0x0=>0x1]	296722	1			T7	189		T16	4544		T22	23
all_pins[2]	transitions[0x1=>0x0]	499182	1			T1	95		T2	285		T3	8