Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336515 |
1 |
|
|
T1 |
65 |
|
T2 |
184 |
|
T3 |
6 |
auto[1] |
3365 |
1 |
|
|
T4 |
1 |
|
T8 |
23 |
|
T9 |
19 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
302641 |
1 |
|
|
T1 |
12 |
|
T2 |
51 |
|
T3 |
4 |
auto[1] |
37239 |
1 |
|
|
T1 |
53 |
|
T2 |
133 |
|
T3 |
2 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326090 |
1 |
|
|
T1 |
65 |
|
T2 |
184 |
|
T34 |
2188 |
auto[1] |
13790 |
1 |
|
|
T3 |
6 |
|
T4 |
1 |
|
T7 |
10 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13790 |
1 |
|
|
T3 |
6 |
|
T4 |
1 |
|
T7 |
10 |
sw_kmac_invalid_sideload |
326090 |
1 |
|
|
T1 |
65 |
|
T2 |
184 |
|
T34 |
2188 |
app_valid_sideload |
13790 |
1 |
|
|
T3 |
6 |
|
T4 |
1 |
|
T7 |
10 |
app_invalid_sideload |
326090 |
1 |
|
|
T1 |
65 |
|
T2 |
184 |
|
T34 |
2188 |