Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10640456 |
1 |
|
|
T1 |
10236 |
|
T2 |
30852 |
|
T3 |
740 |
auto[1] |
10640443 |
1 |
|
|
T1 |
10236 |
|
T2 |
30852 |
|
T3 |
740 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21046363 |
1 |
|
|
T1 |
20374 |
|
T2 |
61436 |
|
T3 |
1472 |
triple_byte_access |
78034 |
1 |
|
|
T1 |
30 |
|
T2 |
88 |
|
T34 |
620 |
halfword_access |
78438 |
1 |
|
|
T1 |
34 |
|
T2 |
88 |
|
T3 |
4 |
byte_access |
78064 |
1 |
|
|
T1 |
34 |
|
T2 |
92 |
|
T3 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10523188 |
1 |
|
|
T1 |
10187 |
|
T2 |
30718 |
|
T3 |
736 |
auto[0] |
triple_byte_access |
39017 |
1 |
|
|
T1 |
15 |
|
T2 |
44 |
|
T34 |
310 |
auto[0] |
halfword_access |
39219 |
1 |
|
|
T1 |
17 |
|
T2 |
44 |
|
T3 |
2 |
auto[0] |
byte_access |
39032 |
1 |
|
|
T1 |
17 |
|
T2 |
46 |
|
T3 |
2 |
auto[1] |
word_access |
10523175 |
1 |
|
|
T1 |
10187 |
|
T2 |
30718 |
|
T3 |
736 |
auto[1] |
triple_byte_access |
39017 |
1 |
|
|
T1 |
15 |
|
T2 |
44 |
|
T34 |
310 |
auto[1] |
halfword_access |
39219 |
1 |
|
|
T1 |
17 |
|
T2 |
44 |
|
T3 |
2 |
auto[1] |
byte_access |
39032 |
1 |
|
|
T1 |
17 |
|
T2 |
46 |
|
T3 |
2 |