Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100183616	1			T1	109316		T17	2375		T18	223650
all_values[1]	100183616	1			T1	109316		T17	2375		T18	223650
all_values[2]	100183616	1			T1	109316		T17	2375		T18	223650

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634064

1

T1

3208

T17

12

T18

6

auto[1]

299916784

1

T1

324740

T17

7113

T18

670944

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299033253

1

T1

327627

T17

6480

T18

669240

auto[1]

1517595

1

T1

321

T17

645

T18

1710

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186307	1			T1	1600		T18	1		T7	152
all_values[0]	auto[0]	auto[1]	2079	1			T1	4		T18	2		T7	2
all_values[0]	auto[1]	auto[0]	99491444	1			T1	107609		T17	2160		T18	223079
all_values[0]	auto[1]	auto[1]	503786	1			T1	103		T17	215		T18	568
all_values[1]	auto[0]	auto[0]	227844	1			T1	1600		T38	66		T40	73
all_values[1]	auto[0]	auto[1]	1690	1			T1	4		T38	5		T40	8
all_values[1]	auto[1]	auto[0]	99449907	1			T1	107609		T17	2160		T18	223080
all_values[1]	auto[1]	auto[1]	504175	1			T1	103		T17	215		T18	570
all_values[2]	auto[0]	auto[0]	214584	1			T17	11		T18	1		T7	1
all_values[2]	auto[0]	auto[1]	1560	1			T17	1		T18	2		T8	20
all_values[2]	auto[1]	auto[0]	99463167	1			T1	109209		T17	2149		T18	223079
all_values[2]	auto[1]	auto[1]	504305	1			T1	107		T17	214		T18	568