Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322946 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T17 |
288 |
auto[1] |
366346 |
1 |
|
|
T1 |
138 |
|
T18 |
778 |
|
T7 |
158 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172515 |
1 |
|
|
T1 |
42 |
|
T17 |
54 |
|
T18 |
169 |
lower_val |
170853 |
1 |
|
|
T1 |
34 |
|
T2 |
1 |
|
T17 |
92 |
zero_val |
1812 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
252648 |
1 |
|
|
T1 |
34 |
|
T17 |
170 |
|
T18 |
180 |
lower_val |
253262 |
1 |
|
|
T1 |
38 |
|
T2 |
2 |
|
T17 |
118 |
zero_val |
183382 |
1 |
|
|
T1 |
68 |
|
T18 |
404 |
|
T7 |
80 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40525 |
1 |
|
|
T17 |
30 |
|
T40 |
5 |
|
T8 |
76 |
higher_val |
higher_val |
auto[1] |
22893 |
1 |
|
|
T1 |
13 |
|
T18 |
43 |
|
T7 |
11 |
higher_val |
lower_val |
auto[0] |
40523 |
1 |
|
|
T17 |
24 |
|
T40 |
3 |
|
T8 |
75 |
higher_val |
lower_val |
auto[1] |
23172 |
1 |
|
|
T1 |
12 |
|
T18 |
44 |
|
T7 |
9 |
higher_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T8 |
2 |
|
T85 |
1 |
|
T41 |
1 |
higher_val |
zero_val |
auto[1] |
45331 |
1 |
|
|
T1 |
17 |
|
T18 |
82 |
|
T7 |
15 |
lower_val |
higher_val |
auto[0] |
39620 |
1 |
|
|
T17 |
61 |
|
T40 |
2 |
|
T8 |
70 |
lower_val |
higher_val |
auto[1] |
22895 |
1 |
|
|
T1 |
6 |
|
T18 |
52 |
|
T7 |
11 |
lower_val |
lower_val |
auto[0] |
40169 |
1 |
|
|
T2 |
1 |
|
T17 |
31 |
|
T18 |
1 |
lower_val |
lower_val |
auto[1] |
22667 |
1 |
|
|
T1 |
8 |
|
T18 |
59 |
|
T7 |
11 |
lower_val |
zero_val |
auto[0] |
86 |
1 |
|
|
T192 |
1 |
|
T35 |
1 |
|
T193 |
1 |
lower_val |
zero_val |
auto[1] |
45416 |
1 |
|
|
T1 |
20 |
|
T18 |
116 |
|
T7 |
20 |
zero_val |
higher_val |
auto[0] |
561 |
1 |
|
|
T7 |
1 |
|
T38 |
1 |
|
T8 |
2 |
zero_val |
higher_val |
auto[1] |
141 |
1 |
|
|
T8 |
2 |
|
T72 |
2 |
|
T66 |
2 |
zero_val |
lower_val |
auto[0] |
537 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[1] |
118 |
1 |
|
|
T18 |
1 |
|
T8 |
2 |
|
T72 |
2 |
zero_val |
zero_val |
auto[0] |
242 |
1 |
|
|
T8 |
2 |
|
T58 |
1 |
|
T85 |
1 |
zero_val |
zero_val |
auto[1] |
213 |
1 |
|
|
T18 |
1 |
|
T72 |
8 |
|
T66 |
2 |