Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	17185081	1			T1	89699		T17	29845		T7	10702
shake	57424944	1			T1	25884		T17	11523		T7	6562
sha3	35293553	1			T1	5176		T17	471		T18	222869

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92717422

1

T1

31060

T17

11994

T18

222869

auto[1]

17186156

1

T1

89699

T17

29845

T7

10704

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	91677839	1			T1	91475		T17	18285		T18	220821
depth[0x01]	3925790	1			T1	5974		T17	3814		T18	2048
depth[0x02]	3574397	1			T1	6307		T17	5512		T7	413
depth[0x03]	3345351	1			T1	6050		T17	4664		T7	382
depth[0x04]	2989537	1			T1	5519		T17	3447		T7	357
depth[0x05]	1722931	1			T1	3194		T17	2544		T7	207
depth[0x06]	542148	1			T1	788		T17	1638		T7	76
depth[0x07]	447682	1			T1	111		T17	593		T7	71
depth[0x08]	440775	1			T1	152		T17	156		T7	92
depth[0x09]	417354	1			T1	105		T17	77		T7	74
depth[0x0a]	819774	1			T1	1084		T17	1109		T7	520

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18225739

1

T1

29284

T17

23554

T18

2048

auto[1]

91677839

1

T1

91475

T17

18285

T18

220821

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109083804

1

T1

119675

T17

40730

T18

222869

auto[1]

819774

1

T1

1084

T17

1109

T7

520