Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100183616	1			T1	109316		T17	2375		T18	223650
all_pins[1]	100183616	1			T1	109316		T17	2375		T18	223650
all_pins[2]	100183616	1			T1	109316		T17	2375		T18	223650

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299736821	1			T1	327812		T17	6910		T18	670382
values[0x1]	814027	1			T1	136		T17	215		T18	568
transitions[0x0=>0x1]	811846	1			T1	136		T17	215		T18	568
transitions[0x1=>0x0]	811872	1			T1	136		T17	215		T18	568

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99679830	1			T1	109213		T17	2160		T18	223082
all_pins[0]	values[0x1]	503786	1			T1	103		T17	215		T18	568
all_pins[0]	transitions[0x0=>0x1]	503771	1			T1	103		T17	215		T18	568
all_pins[0]	transitions[0x1=>0x0]	6429	1			T1	33		T7	21		T60	2
all_pins[1]	values[0x0]	100177172	1			T1	109283		T17	2375		T18	223650
all_pins[1]	values[0x1]	6444	1			T1	33		T7	21		T60	2
all_pins[1]	transitions[0x0=>0x1]	6135	1			T1	33		T7	21		T60	2
all_pins[1]	transitions[0x1=>0x0]	303488	1			T14	17006		T19	1054		T23	542
all_pins[2]	values[0x0]	99879819	1			T1	109316		T17	2375		T18	223650
all_pins[2]	values[0x1]	303797	1			T14	17006		T19	1054		T23	542
all_pins[2]	transitions[0x0=>0x1]	301940	1			T14	16897		T19	1053		T23	542
all_pins[2]	transitions[0x1=>0x0]	501955	1			T1	103		T17	215		T18	568