Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	674	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5555	1			T1	7		T17	22		T7	8
len_601_800	12579	1			T1	21		T17	47		T7	19
len_401_600	8329	1			T1	22		T17	35		T7	14
len_201_400	16466	1			T1	8		T17	22		T7	8
len_65_200	73163	1			T1	6		T17	12		T7	4
len_min_for_xof_require_squeeze	995	1			T72	10		T66	9		T70	1
len_keccak_block_sizes[72]	761	1			T17	1		T36	1		T42	1
len_keccak_block_sizes[104]	744	1			T1	1		T72	5		T66	9
len_keccak_block_sizes[136]	746	1			T72	5		T66	9		T70	2
len_keccak_block_sizes[144]	281	1			T72	5		T194	5		T195	5
len_keccak_block_sizes[168]	272	1			T72	5		T196	1		T194	5
len_datapath_width	14010	1			T1	1		T17	1		T38	3
len_2_63	212192	1			T1	5		T17	3		T18	390
len_1	53	1			T196	1		T16	1		T197	1