Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10723981 |
1 |
|
|
T1 |
10593 |
|
T17 |
22552 |
|
T18 |
2730 |
auto[1] |
10723952 |
1 |
|
|
T1 |
10593 |
|
T17 |
22552 |
|
T18 |
2730 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21211503 |
1 |
|
|
T1 |
21086 |
|
T17 |
44888 |
|
T18 |
5460 |
triple_byte_access |
78750 |
1 |
|
|
T1 |
48 |
|
T17 |
70 |
|
T7 |
38 |
halfword_access |
79194 |
1 |
|
|
T1 |
30 |
|
T17 |
82 |
|
T7 |
18 |
byte_access |
78486 |
1 |
|
|
T1 |
22 |
|
T17 |
64 |
|
T7 |
20 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10605766 |
1 |
|
|
T1 |
10543 |
|
T17 |
22444 |
|
T18 |
2730 |
auto[0] |
triple_byte_access |
39375 |
1 |
|
|
T1 |
24 |
|
T17 |
35 |
|
T7 |
19 |
auto[0] |
halfword_access |
39597 |
1 |
|
|
T1 |
15 |
|
T17 |
41 |
|
T7 |
9 |
auto[0] |
byte_access |
39243 |
1 |
|
|
T1 |
11 |
|
T17 |
32 |
|
T7 |
10 |
auto[1] |
word_access |
10605737 |
1 |
|
|
T1 |
10543 |
|
T17 |
22444 |
|
T18 |
2730 |
auto[1] |
triple_byte_access |
39375 |
1 |
|
|
T1 |
24 |
|
T17 |
35 |
|
T7 |
19 |
auto[1] |
halfword_access |
39597 |
1 |
|
|
T1 |
15 |
|
T17 |
41 |
|
T7 |
9 |
auto[1] |
byte_access |
39243 |
1 |
|
|
T1 |
11 |
|
T17 |
32 |
|
T7 |
10 |