Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98524365	1			T1	163109		T2	573789		T3	160357
all_values[1]	98524365	1			T1	163109		T2	573789		T3	160357
all_values[2]	98524365	1			T1	163109		T2	573789		T3	160357

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

470333

1

T1

15

T2

21

T3

23

auto[1]

295102762

1

T1

489312

T2

172134

T3

481048

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294063933

1

T1

487911

T2

171080

T3

479658

auto[1]

1509162

1

T1

1416

T2

10566

T3

1413

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	163951	1			T2	3		T3	10		T37	3
all_values[0]	auto[0]	auto[1]	2111	1			T2	4		T3	10		T37	4
all_values[0]	auto[1]	auto[0]	97857360	1			T1	162637		T2	570264		T3	159876
all_values[0]	auto[1]	auto[1]	500943	1			T1	472		T2	3518		T3	461
all_values[1]	auto[0]	auto[0]	146375	1			T1	2		T2	6		T37	6
all_values[1]	auto[0]	auto[1]	1458	1			T1	1		T2	5		T37	5
all_values[1]	auto[1]	auto[0]	97874936	1			T1	162635		T2	570261		T3	159886
all_values[1]	auto[1]	auto[1]	501596	1			T1	471		T2	3517		T3	471
all_values[2]	auto[0]	auto[0]	154776	1			T1	7		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1662	1			T1	5		T2	2		T3	2
all_values[2]	auto[1]	auto[0]	97866535	1			T1	162630		T2	570266		T3	159885
all_values[2]	auto[1]	auto[1]	501392	1			T1	467		T2	3520		T3	469