Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
382714 |
1 |
|
|
T1 |
620 |
|
T2 |
4674 |
|
T3 |
620 |
auto[1] |
302230 |
1 |
|
|
T37 |
4528 |
|
T34 |
16 |
|
T7 |
64 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171842 |
1 |
|
|
T1 |
186 |
|
T2 |
1200 |
|
T3 |
142 |
lower_val |
169422 |
1 |
|
|
T1 |
128 |
|
T2 |
1208 |
|
T3 |
158 |
zero_val |
1787 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
266408 |
1 |
|
|
T1 |
296 |
|
T2 |
2360 |
|
T3 |
298 |
lower_val |
267402 |
1 |
|
|
T1 |
324 |
|
T2 |
2314 |
|
T3 |
322 |
zero_val |
151134 |
1 |
|
|
T37 |
2236 |
|
T34 |
12 |
|
T7 |
32 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48038 |
1 |
|
|
T1 |
92 |
|
T2 |
601 |
|
T3 |
82 |
higher_val |
higher_val |
auto[1] |
19004 |
1 |
|
|
T37 |
283 |
|
T7 |
5 |
|
T8 |
20 |
higher_val |
lower_val |
auto[0] |
48034 |
1 |
|
|
T1 |
94 |
|
T2 |
599 |
|
T3 |
60 |
higher_val |
lower_val |
auto[1] |
19094 |
1 |
|
|
T37 |
279 |
|
T7 |
3 |
|
T43 |
1 |
higher_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T34 |
1 |
|
T7 |
2 |
|
T9 |
1 |
higher_val |
zero_val |
auto[1] |
37591 |
1 |
|
|
T37 |
551 |
|
T34 |
1 |
|
T7 |
7 |
lower_val |
higher_val |
auto[0] |
47084 |
1 |
|
|
T1 |
60 |
|
T2 |
608 |
|
T3 |
72 |
lower_val |
higher_val |
auto[1] |
18714 |
1 |
|
|
T37 |
304 |
|
T34 |
1 |
|
T7 |
5 |
lower_val |
lower_val |
auto[0] |
47055 |
1 |
|
|
T1 |
68 |
|
T2 |
600 |
|
T3 |
86 |
lower_val |
lower_val |
auto[1] |
18964 |
1 |
|
|
T37 |
282 |
|
T34 |
1 |
|
T7 |
7 |
lower_val |
zero_val |
auto[0] |
61 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T57 |
1 |
lower_val |
zero_val |
auto[1] |
37544 |
1 |
|
|
T37 |
610 |
|
T34 |
4 |
|
T7 |
5 |
zero_val |
higher_val |
auto[0] |
577 |
1 |
|
|
T2 |
3 |
|
T37 |
1 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
115 |
1 |
|
|
T37 |
1 |
|
T56 |
2 |
|
T139 |
4 |
zero_val |
lower_val |
auto[0] |
586 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
98 |
1 |
|
|
T37 |
1 |
|
T7 |
1 |
|
T56 |
1 |
zero_val |
zero_val |
auto[0] |
231 |
1 |
|
|
T34 |
1 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
zero_val |
auto[1] |
180 |
1 |
|
|
T37 |
2 |
|
T9 |
2 |
|
T56 |
3 |