Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98524365	1			T1	163109		T2	573789		T3	160357
all_pins[1]	98524365	1			T1	163109		T2	573789		T3	160357
all_pins[2]	98524365	1			T1	163109		T2	573789		T3	160357

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	294795413	1			T1	488855		T2	171784		T3	480610
values[0x1]	777682	1			T1	472		T2	3518		T3	461
transitions[0x0=>0x1]	775744	1			T1	472		T2	3518		T3	461
transitions[0x1=>0x0]	775773	1			T1	472		T2	3518		T3	461

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98023422	1			T1	162637		T2	570271		T3	159896
all_pins[0]	values[0x1]	500943	1			T1	472		T2	3518		T3	461
all_pins[0]	transitions[0x0=>0x1]	500933	1			T1	472		T2	3518		T3	461
all_pins[0]	transitions[0x1=>0x0]	6760	1			T35	2		T8	55		T9	22
all_pins[1]	values[0x0]	98517595	1			T1	163109		T2	573789		T3	160357
all_pins[1]	values[0x1]	6770	1			T35	2		T8	55		T9	22
all_pins[1]	transitions[0x0=>0x1]	6447	1			T35	2		T8	55		T9	22
all_pins[1]	transitions[0x1=>0x0]	269646	1			T21	728		T16	3706		T17	633
all_pins[2]	values[0x0]	98254396	1			T1	163109		T2	573789		T3	160357
all_pins[2]	values[0x1]	269969	1			T21	728		T16	3706		T17	633
all_pins[2]	transitions[0x0=>0x1]	268364	1			T21	728		T16	3682		T17	629
all_pins[2]	transitions[0x1=>0x0]	499367	1			T1	472		T2	3518		T3	461