Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10595550 |
1 |
|
|
T1 |
3720 |
|
T2 |
27235 |
|
T3 |
3720 |
auto[1] |
10595537 |
1 |
|
|
T1 |
3720 |
|
T2 |
27235 |
|
T3 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20956365 |
1 |
|
|
T1 |
7440 |
|
T2 |
52796 |
|
T3 |
7440 |
triple_byte_access |
78208 |
1 |
|
|
T2 |
558 |
|
T37 |
620 |
|
T36 |
74 |
halfword_access |
78498 |
1 |
|
|
T2 |
558 |
|
T37 |
632 |
|
T36 |
76 |
byte_access |
78016 |
1 |
|
|
T2 |
558 |
|
T37 |
620 |
|
T36 |
52 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10478189 |
1 |
|
|
T1 |
3720 |
|
T2 |
26398 |
|
T3 |
3720 |
auto[0] |
triple_byte_access |
39104 |
1 |
|
|
T2 |
279 |
|
T37 |
310 |
|
T36 |
37 |
auto[0] |
halfword_access |
39249 |
1 |
|
|
T2 |
279 |
|
T37 |
316 |
|
T36 |
38 |
auto[0] |
byte_access |
39008 |
1 |
|
|
T2 |
279 |
|
T37 |
310 |
|
T36 |
26 |
auto[1] |
word_access |
10478176 |
1 |
|
|
T1 |
3720 |
|
T2 |
26398 |
|
T3 |
3720 |
auto[1] |
triple_byte_access |
39104 |
1 |
|
|
T2 |
279 |
|
T37 |
310 |
|
T36 |
37 |
auto[1] |
halfword_access |
39249 |
1 |
|
|
T2 |
279 |
|
T37 |
316 |
|
T36 |
38 |
auto[1] |
byte_access |
39008 |
1 |
|
|
T2 |
279 |
|
T37 |
310 |
|
T36 |
26 |