Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 269 1 T158 4 T159 4 T160 7
all_values[1] 269 1 T158 4 T159 4 T160 7
all_values[2] 269 1 T158 4 T159 4 T160 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 430 1 T158 8 T159 7 T160 14
auto[1] 377 1 T158 4 T159 5 T160 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 380 1 T158 8 T159 6 T160 12
auto[1] 427 1 T158 4 T159 6 T160 9


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T158 9 T159 7 T160 15
auto[1] 326 1 T158 3 T159 5 T160 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T158 2 T159 1 T160 2
all_values[0] auto[0] auto[0] auto[1] 21 1 T160 1 T199 2 T200 1
all_values[0] auto[0] auto[1] auto[0] 55 1 T158 2 T159 1 T160 1
all_values[0] auto[0] auto[1] auto[1] 30 1 T159 1 T201 2 T202 1
all_values[0] auto[1] auto[0] auto[1] 49 1 T160 2 T201 2 T199 4
all_values[0] auto[1] auto[1] auto[1] 50 1 T159 1 T160 1 T199 1
all_values[1] auto[0] auto[0] auto[0] 91 1 T158 2 T159 2 T160 4
all_values[1] auto[0] auto[1] auto[0] 76 1 T160 2 T201 1 T199 1
all_values[1] auto[1] auto[0] auto[1] 59 1 T158 2 T160 1 T201 2
all_values[1] auto[1] auto[1] auto[1] 43 1 T159 2 T201 1 T203 1
all_values[2] auto[0] auto[0] auto[0] 57 1 T158 2 T159 2 T160 1
all_values[2] auto[0] auto[0] auto[1] 24 1 T160 2 T204 1 T205 2
all_values[2] auto[0] auto[1] auto[0] 37 1 T160 2 T199 1 T202 1
all_values[2] auto[0] auto[1] auto[1] 26 1 T158 1 T201 1 T199 1
all_values[2] auto[1] auto[0] auto[1] 65 1 T159 2 T160 1 T201 2
all_values[2] auto[1] auto[1] auto[1] 60 1 T158 1 T160 1 T201 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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