Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99819666	1			T1	163268		T2	60787		T3	566339
all_values[1]	99819666	1			T1	163268		T2	60787		T3	566339
all_values[2]	99819666	1			T1	163268		T2	60787		T3	566339

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577974

1

T1

3

T2

1478

T3

18

auto[1]

298881024

1

T1

489801

T2

180883

T3

169899

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297930645

1

T1

488412

T2

181233

T3

168862

auto[1]

1528353

1

T1

1392

T2

1128

T3

10395

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	190991	1			T2	561		T32	4		T35	1
all_values[0]	auto[0]	auto[1]	2022	1			T2	14		T32	2		T35	2
all_values[0]	auto[1]	auto[0]	99119224	1			T1	162804		T2	59850		T3	562874
all_values[0]	auto[1]	auto[1]	507429	1			T1	464		T2	362		T3	3465
all_values[1]	auto[0]	auto[0]	188737	1			T1	2		T2	317		T3	2
all_values[1]	auto[0]	auto[1]	1502	1			T1	1		T2	7		T3	1
all_values[1]	auto[1]	auto[0]	99121478	1			T1	162802		T2	60094		T3	562872
all_values[1]	auto[1]	auto[1]	507949	1			T1	463		T2	369		T3	3464
all_values[2]	auto[0]	auto[0]	193169	1			T2	576		T3	10		T32	4
all_values[2]	auto[0]	auto[1]	1553	1			T2	3		T3	5		T32	2
all_values[2]	auto[1]	auto[0]	99117046	1			T1	162804		T2	59835		T3	562864
all_values[2]	auto[1]	auto[1]	507898	1			T1	464		T2	373		T3	3460