Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
362392 |
1 |
|
|
T1 |
2 |
|
T2 |
190 |
|
T3 |
2 |
auto[1] |
330204 |
1 |
|
|
T1 |
618 |
|
T2 |
408 |
|
T3 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173714 |
1 |
|
|
T1 |
142 |
|
T2 |
136 |
|
T3 |
1129 |
lower_val |
171106 |
1 |
|
|
T1 |
155 |
|
T2 |
168 |
|
T3 |
1204 |
zero_val |
1841 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263886 |
1 |
|
|
T1 |
164 |
|
T2 |
222 |
|
T3 |
1142 |
lower_val |
263892 |
1 |
|
|
T1 |
134 |
|
T2 |
180 |
|
T3 |
1102 |
zero_val |
164818 |
1 |
|
|
T1 |
322 |
|
T2 |
196 |
|
T3 |
2430 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45613 |
1 |
|
|
T2 |
25 |
|
T33 |
1 |
|
T43 |
3 |
higher_val |
higher_val |
auto[1] |
20781 |
1 |
|
|
T1 |
38 |
|
T2 |
21 |
|
T3 |
255 |
higher_val |
lower_val |
auto[0] |
45148 |
1 |
|
|
T2 |
17 |
|
T33 |
1 |
|
T43 |
5 |
higher_val |
lower_val |
auto[1] |
20867 |
1 |
|
|
T1 |
28 |
|
T2 |
23 |
|
T3 |
276 |
higher_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T2 |
1 |
|
T9 |
1 |
|
T38 |
1 |
higher_val |
zero_val |
auto[1] |
41229 |
1 |
|
|
T1 |
76 |
|
T2 |
49 |
|
T3 |
598 |
lower_val |
higher_val |
auto[0] |
44831 |
1 |
|
|
T2 |
30 |
|
T3 |
1 |
|
T32 |
1 |
lower_val |
higher_val |
auto[1] |
20422 |
1 |
|
|
T1 |
42 |
|
T2 |
38 |
|
T3 |
288 |
lower_val |
lower_val |
auto[0] |
44204 |
1 |
|
|
T2 |
17 |
|
T33 |
3 |
|
T79 |
79 |
lower_val |
lower_val |
auto[1] |
20879 |
1 |
|
|
T1 |
37 |
|
T2 |
28 |
|
T3 |
301 |
lower_val |
zero_val |
auto[0] |
54 |
1 |
|
|
T2 |
1 |
|
T8 |
1 |
|
T189 |
1 |
lower_val |
zero_val |
auto[1] |
40716 |
1 |
|
|
T1 |
76 |
|
T2 |
54 |
|
T3 |
614 |
zero_val |
higher_val |
auto[0] |
591 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T32 |
1 |
zero_val |
higher_val |
auto[1] |
115 |
1 |
|
|
T3 |
2 |
|
T34 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[0] |
555 |
1 |
|
|
T2 |
1 |
|
T33 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[1] |
133 |
1 |
|
|
T2 |
2 |
|
T35 |
5 |
|
T190 |
1 |
zero_val |
zero_val |
auto[0] |
221 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
zero_val |
auto[1] |
226 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T34 |
3 |