Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99819666	1			T1	163268		T2	60787		T3	566339
all_pins[1]	99819666	1			T1	163268		T2	60787		T3	566339
all_pins[2]	99819666	1			T1	163268		T2	60787		T3	566339

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298619953	1			T1	489340		T2	177032		T3	169555
values[0x1]	839045	1			T1	464		T2	5329		T3	3465
transitions[0x0=>0x1]	836810	1			T1	464		T2	5277		T3	3465
transitions[0x1=>0x0]	836845	1			T1	464		T2	5277		T3	3465

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99312237	1			T1	162804		T2	60425		T3	562874
all_pins[0]	values[0x1]	507429	1			T1	464		T2	362		T3	3465
all_pins[0]	transitions[0x0=>0x1]	507420	1			T1	464		T2	362		T3	3465
all_pins[0]	transitions[0x1=>0x0]	5749	1			T2	46		T18	8		T39	3
all_pins[1]	values[0x0]	99813908	1			T1	163268		T2	60741		T3	566339
all_pins[1]	values[0x1]	5758	1			T2	46		T18	8		T39	3
all_pins[1]	transitions[0x0=>0x1]	5534	1			T2	37		T18	8		T39	3
all_pins[1]	transitions[0x1=>0x0]	325634	1			T2	4912		T9	633		T21	303
all_pins[2]	values[0x0]	99493808	1			T1	163268		T2	55866		T3	566339
all_pins[2]	values[0x1]	325858	1			T2	4921		T9	633		T21	303
all_pins[2]	transitions[0x0=>0x1]	323856	1			T2	4878		T9	633		T21	303
all_pins[2]	transitions[0x1=>0x0]	505462	1			T1	464		T2	319		T3	3465