Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10648118 |
1 |
|
|
T1 |
3720 |
|
T2 |
32984 |
|
T3 |
27235 |
auto[1] |
10648046 |
1 |
|
|
T1 |
3720 |
|
T2 |
32984 |
|
T3 |
27235 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21058580 |
1 |
|
|
T1 |
7440 |
|
T2 |
65638 |
|
T3 |
52796 |
triple_byte_access |
79154 |
1 |
|
|
T2 |
96 |
|
T3 |
558 |
|
T32 |
38 |
halfword_access |
79368 |
1 |
|
|
T2 |
94 |
|
T3 |
558 |
|
T32 |
36 |
byte_access |
79062 |
1 |
|
|
T2 |
140 |
|
T3 |
558 |
|
T32 |
58 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10529326 |
1 |
|
|
T1 |
3720 |
|
T2 |
32819 |
|
T3 |
26398 |
auto[0] |
triple_byte_access |
39577 |
1 |
|
|
T2 |
48 |
|
T3 |
279 |
|
T32 |
19 |
auto[0] |
halfword_access |
39684 |
1 |
|
|
T2 |
47 |
|
T3 |
279 |
|
T32 |
18 |
auto[0] |
byte_access |
39531 |
1 |
|
|
T2 |
70 |
|
T3 |
279 |
|
T32 |
29 |
auto[1] |
word_access |
10529254 |
1 |
|
|
T1 |
3720 |
|
T2 |
32819 |
|
T3 |
26398 |
auto[1] |
triple_byte_access |
39577 |
1 |
|
|
T2 |
48 |
|
T3 |
279 |
|
T32 |
19 |
auto[1] |
halfword_access |
39684 |
1 |
|
|
T2 |
47 |
|
T3 |
279 |
|
T32 |
18 |
auto[1] |
byte_access |
39531 |
1 |
|
|
T2 |
70 |
|
T3 |
279 |
|
T32 |
29 |