Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99075388	1			T1	458678		T2	13962		T3	12863
all_values[1]	99075388	1			T1	458678		T2	13962		T3	12863
all_values[2]	99075388	1			T1	458678		T2	13962		T3	12863

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

457744

1

T1

7

T2

1

T3

12

auto[1]

296768420

1

T1

137602

T2

41885

T3

38577

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295706208

1

T1

136585

T2

41421

T3

38199

auto[1]

1519956

1

T1

10182

T2

465

T3

390

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142213	1			T1	3		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	1916	1			T1	4		T32	4		T34	2
all_values[0]	auto[1]	auto[0]	98426523	1			T1	455281		T2	13806		T3	12732
all_values[0]	auto[1]	auto[1]	504736	1			T1	3390		T2	155		T3	130
all_values[1]	auto[0]	auto[0]	147678	1			T3	9		T31	5		T33	2
all_values[1]	auto[0]	auto[1]	1551	1			T3	1		T31	2		T33	1
all_values[1]	auto[1]	auto[0]	98421058	1			T1	455284		T2	13807		T3	12724
all_values[1]	auto[1]	auto[1]	505101	1			T1	3394		T2	155		T3	129
all_values[2]	auto[0]	auto[0]	162984	1			T3	1		T32	5		T93	2
all_values[2]	auto[0]	auto[1]	1402	1			T32	2		T93	1		T39	2
all_values[2]	auto[1]	auto[0]	98405752	1			T1	455284		T2	13807		T3	12732
all_values[2]	auto[1]	auto[1]	505250	1			T1	3394		T2	155		T3	130