Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323482 |
1 |
|
|
T1 |
2 |
|
T2 |
266 |
|
T3 |
284 |
auto[1] |
364704 |
1 |
|
|
T1 |
4528 |
|
T30 |
618 |
|
T31 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172531 |
1 |
|
|
T1 |
1129 |
|
T2 |
54 |
|
T3 |
89 |
lower_val |
170110 |
1 |
|
|
T1 |
1146 |
|
T2 |
74 |
|
T3 |
56 |
zero_val |
1808 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
252796 |
1 |
|
|
T1 |
1168 |
|
T2 |
128 |
|
T3 |
138 |
lower_val |
252150 |
1 |
|
|
T1 |
1118 |
|
T2 |
138 |
|
T3 |
146 |
zero_val |
183240 |
1 |
|
|
T1 |
2244 |
|
T30 |
336 |
|
T31 |
2232 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40463 |
1 |
|
|
T2 |
26 |
|
T3 |
37 |
|
T7 |
9 |
higher_val |
higher_val |
auto[1] |
23020 |
1 |
|
|
T1 |
308 |
|
T30 |
32 |
|
T31 |
278 |
higher_val |
lower_val |
auto[0] |
40370 |
1 |
|
|
T2 |
28 |
|
T3 |
52 |
|
T7 |
14 |
higher_val |
lower_val |
auto[1] |
22801 |
1 |
|
|
T1 |
271 |
|
T30 |
30 |
|
T31 |
281 |
higher_val |
zero_val |
auto[0] |
77 |
1 |
|
|
T94 |
1 |
|
T11 |
1 |
|
T193 |
1 |
higher_val |
zero_val |
auto[1] |
45800 |
1 |
|
|
T1 |
550 |
|
T30 |
92 |
|
T31 |
565 |
lower_val |
higher_val |
auto[0] |
39863 |
1 |
|
|
T2 |
35 |
|
T3 |
25 |
|
T7 |
17 |
lower_val |
higher_val |
auto[1] |
22544 |
1 |
|
|
T1 |
283 |
|
T30 |
33 |
|
T31 |
265 |
lower_val |
lower_val |
auto[0] |
39893 |
1 |
|
|
T2 |
39 |
|
T3 |
31 |
|
T7 |
11 |
lower_val |
lower_val |
auto[1] |
22306 |
1 |
|
|
T1 |
302 |
|
T30 |
49 |
|
T31 |
266 |
lower_val |
zero_val |
auto[0] |
65 |
1 |
|
|
T194 |
1 |
|
T48 |
1 |
|
T195 |
1 |
lower_val |
zero_val |
auto[1] |
45439 |
1 |
|
|
T1 |
561 |
|
T30 |
87 |
|
T31 |
552 |
zero_val |
higher_val |
auto[0] |
564 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
134 |
1 |
|
|
T1 |
1 |
|
T196 |
5 |
|
T195 |
2 |
zero_val |
lower_val |
auto[0] |
506 |
1 |
|
|
T7 |
1 |
|
T32 |
1 |
|
T33 |
1 |
zero_val |
lower_val |
auto[1] |
147 |
1 |
|
|
T31 |
1 |
|
T196 |
2 |
|
T197 |
1 |
zero_val |
zero_val |
auto[0] |
241 |
1 |
|
|
T51 |
1 |
|
T36 |
1 |
|
T52 |
1 |
zero_val |
zero_val |
auto[1] |
216 |
1 |
|
|
T1 |
1 |
|
T31 |
1 |
|
T196 |
3 |