Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99075388	1			T1	458678		T2	13962		T3	12863
all_pins[1]	99075388	1			T1	458678		T2	13962		T3	12863
all_pins[2]	99075388	1			T1	458678		T2	13962		T3	12863

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296411087	1			T1	137264		T2	41731		T3	38459
values[0x1]	815077	1			T1	3390		T2	155		T3	130
transitions[0x0=>0x1]	813031	1			T1	3390		T2	155		T3	130
transitions[0x1=>0x0]	813053	1			T1	3390		T2	155		T3	130

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98570652	1			T1	455288		T2	13807		T3	12733
all_pins[0]	values[0x1]	504736	1			T1	3390		T2	155		T3	130
all_pins[0]	transitions[0x0=>0x1]	504725	1			T1	3390		T2	155		T3	130
all_pins[0]	transitions[0x1=>0x0]	5518	1			T7	11		T34	6		T36	1
all_pins[1]	values[0x0]	99069859	1			T1	458678		T2	13962		T3	12863
all_pins[1]	values[0x1]	5529	1			T7	11		T34	6		T36	1
all_pins[1]	transitions[0x0=>0x1]	5317	1			T7	11		T34	6		T36	1
all_pins[1]	transitions[0x1=>0x0]	304600	1			T19	376		T64	536		T65	639
all_pins[2]	values[0x0]	98770576	1			T1	458678		T2	13962		T3	12863
all_pins[2]	values[0x1]	304812	1			T19	376		T64	536		T65	639
all_pins[2]	transitions[0x0=>0x1]	302989	1			T19	375		T64	536		T65	639
all_pins[2]	transitions[0x1=>0x0]	502935	1			T1	3390		T2	155		T3	130