Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10361641 |
1 |
|
|
T1 |
47900 |
|
T2 |
18083 |
|
T3 |
15849 |
auto[1] |
10361610 |
1 |
|
|
T1 |
47900 |
|
T2 |
18083 |
|
T3 |
15849 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20488037 |
1 |
|
|
T1 |
93928 |
|
T2 |
36016 |
|
T3 |
31588 |
triple_byte_access |
78376 |
1 |
|
|
T1 |
620 |
|
T2 |
40 |
|
T3 |
38 |
halfword_access |
78724 |
1 |
|
|
T1 |
632 |
|
T2 |
50 |
|
T3 |
40 |
byte_access |
78114 |
1 |
|
|
T1 |
620 |
|
T2 |
60 |
|
T3 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10244034 |
1 |
|
|
T1 |
46964 |
|
T2 |
18008 |
|
T3 |
15794 |
auto[0] |
triple_byte_access |
39188 |
1 |
|
|
T1 |
310 |
|
T2 |
20 |
|
T3 |
19 |
auto[0] |
halfword_access |
39362 |
1 |
|
|
T1 |
316 |
|
T2 |
25 |
|
T3 |
20 |
auto[0] |
byte_access |
39057 |
1 |
|
|
T1 |
310 |
|
T2 |
30 |
|
T3 |
16 |
auto[1] |
word_access |
10244003 |
1 |
|
|
T1 |
46964 |
|
T2 |
18008 |
|
T3 |
15794 |
auto[1] |
triple_byte_access |
39188 |
1 |
|
|
T1 |
310 |
|
T2 |
20 |
|
T3 |
19 |
auto[1] |
halfword_access |
39362 |
1 |
|
|
T1 |
316 |
|
T2 |
25 |
|
T3 |
20 |
auto[1] |
byte_access |
39057 |
1 |
|
|
T1 |
310 |
|
T2 |
30 |
|
T3 |
16 |