Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98275363	1			T1	21731		T2	470455		T3	121550
all_values[1]	98275363	1			T1	21731		T2	470455		T3	121550
all_values[2]	98275363	1			T1	21731		T2	470455		T3	121550

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514059

1

T1

525

T2

3

T3

1975

auto[1]

294312030

1

T1

64668

T2

141136

T3

362675

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293320509

1

T1

64548

T2

140104

T3

364323

auto[1]

1505580

1

T1

645

T2

10323

T3

327

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	151130	1			T1	491		T34	3		T7	12
all_values[0]	auto[0]	auto[1]	1929	1			T1	6		T34	4		T7	2
all_values[0]	auto[1]	auto[0]	97622373	1			T1	21025		T2	467014		T3	121441
all_values[0]	auto[1]	auto[1]	499931	1			T1	209		T2	3441		T3	109
all_values[1]	auto[0]	auto[0]	161601	1			T1	26		T2	2		T34	1
all_values[1]	auto[0]	auto[1]	1455	1			T1	2		T2	1		T34	2
all_values[1]	auto[1]	auto[0]	97611902	1			T1	21490		T2	467012		T3	121441
all_values[1]	auto[1]	auto[1]	500405	1			T1	213		T2	3440		T3	109
all_values[2]	auto[0]	auto[0]	196316	1			T3	1974		T34	3		T37	2
all_values[2]	auto[0]	auto[1]	1628	1			T3	1		T34	4		T37	1
all_values[2]	auto[1]	auto[0]	97577187	1			T1	21516		T2	467014		T3	119467
all_values[2]	auto[1]	auto[1]	500232	1			T1	215		T2	3441		T3	108