Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348726 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
333850 |
1 |
|
|
T1 |
294 |
|
T2 |
4528 |
|
T3 |
148 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
170282 |
1 |
|
|
T1 |
70 |
|
T2 |
1086 |
|
T3 |
32 |
lower_val |
169014 |
1 |
|
|
T1 |
70 |
|
T2 |
1110 |
|
T3 |
41 |
zero_val |
1790 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
257004 |
1 |
|
|
T1 |
60 |
|
T2 |
1082 |
|
T3 |
36 |
lower_val |
258142 |
1 |
|
|
T1 |
92 |
|
T2 |
1144 |
|
T3 |
38 |
zero_val |
167430 |
1 |
|
|
T1 |
144 |
|
T2 |
2304 |
|
T3 |
76 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43082 |
1 |
|
|
T7 |
14 |
|
T37 |
88 |
|
T20 |
21 |
higher_val |
higher_val |
auto[1] |
20907 |
1 |
|
|
T1 |
15 |
|
T2 |
262 |
|
T3 |
13 |
higher_val |
lower_val |
auto[0] |
43484 |
1 |
|
|
T7 |
9 |
|
T37 |
104 |
|
T20 |
20 |
higher_val |
lower_val |
auto[1] |
20945 |
1 |
|
|
T1 |
21 |
|
T2 |
275 |
|
T3 |
1 |
higher_val |
zero_val |
auto[0] |
94 |
1 |
|
|
T3 |
1 |
|
T39 |
1 |
|
T16 |
1 |
higher_val |
zero_val |
auto[1] |
41770 |
1 |
|
|
T1 |
34 |
|
T2 |
549 |
|
T3 |
17 |
lower_val |
higher_val |
auto[0] |
42962 |
1 |
|
|
T7 |
8 |
|
T37 |
94 |
|
T35 |
1 |
lower_val |
higher_val |
auto[1] |
20894 |
1 |
|
|
T1 |
13 |
|
T2 |
276 |
|
T3 |
9 |
lower_val |
lower_val |
auto[0] |
43336 |
1 |
|
|
T7 |
14 |
|
T37 |
93 |
|
T35 |
5 |
lower_val |
lower_val |
auto[1] |
20508 |
1 |
|
|
T1 |
21 |
|
T2 |
262 |
|
T3 |
12 |
lower_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T2 |
1 |
|
T38 |
1 |
|
T41 |
1 |
lower_val |
zero_val |
auto[1] |
41224 |
1 |
|
|
T1 |
36 |
|
T2 |
571 |
|
T3 |
20 |
zero_val |
higher_val |
auto[0] |
519 |
1 |
|
|
T7 |
1 |
|
T37 |
2 |
|
T40 |
1 |
zero_val |
higher_val |
auto[1] |
122 |
1 |
|
|
T34 |
1 |
|
T40 |
1 |
|
T16 |
2 |
zero_val |
lower_val |
auto[0] |
530 |
1 |
|
|
T1 |
1 |
|
T37 |
1 |
|
T35 |
1 |
zero_val |
lower_val |
auto[1] |
129 |
1 |
|
|
T2 |
1 |
|
T74 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[0] |
270 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T34 |
1 |
zero_val |
zero_val |
auto[1] |
220 |
1 |
|
|
T2 |
3 |
|
T34 |
1 |
|
T40 |
1 |