Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98275363	1			T1	21731		T2	470455		T3	121550
all_pins[1]	98275363	1			T1	21731		T2	470455		T3	121550
all_pins[2]	98275363	1			T1	21731		T2	470455		T3	121550

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	293989749	1			T1	64917		T2	140792		T3	364541
values[0x1]	836340	1			T1	276		T2	3441		T3	109
transitions[0x0=>0x1]	834071	1			T1	276		T2	3441		T3	109
transitions[0x1=>0x0]	834089	1			T1	276		T2	3441		T3	109

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97775432	1			T1	21522		T2	467014		T3	121441
all_pins[0]	values[0x1]	499931	1			T1	209		T2	3441		T3	109
all_pins[0]	transitions[0x0=>0x1]	499908	1			T1	209		T2	3441		T3	109
all_pins[0]	transitions[0x1=>0x0]	5679	1			T1	67		T20	43		T8	8
all_pins[1]	values[0x0]	98269661	1			T1	21664		T2	470455		T3	121550
all_pins[1]	values[0x1]	5702	1			T1	67		T20	43		T8	8
all_pins[1]	transitions[0x0=>0x1]	5479	1			T1	67		T20	43		T8	8
all_pins[1]	transitions[0x1=>0x0]	330484	1			T16	1		T21	175		T22	270
all_pins[2]	values[0x0]	97944656	1			T1	21731		T2	470455		T3	121550
all_pins[2]	values[0x1]	330707	1			T16	1		T21	175		T22	270
all_pins[2]	transitions[0x0=>0x1]	328684	1			T16	1		T21	175		T22	270
all_pins[2]	transitions[0x1=>0x0]	497926	1			T1	209		T2	3441		T3	109