Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	678	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5293	1			T1	15		T3	10		T38	2
len_601_800	12057	1			T1	55		T3	28		T7	9
len_401_600	8105	1			T1	42		T3	20		T7	8
len_201_400	15872	1			T1	13		T2	251		T3	3
len_65_200	72431	1			T1	10		T2	680		T3	8
len_min_for_xof_require_squeeze	986	1			T2	10		T40	10		T198	10
len_keccak_block_sizes[72]	751	1			T2	5		T40	5		T198	5
len_keccak_block_sizes[104]	745	1			T2	5		T40	5		T21	1
len_keccak_block_sizes[136]	737	1			T2	5		T40	5		T198	5
len_keccak_block_sizes[144]	274	1			T2	5		T39	1		T40	5
len_keccak_block_sizes[168]	282	1			T2	5		T3	1		T40	5
len_datapath_width	13775	1			T1	1		T2	5		T3	1
len_2_63	211447	1			T1	7		T2	1329		T3	4
len_1	69	1			T16	1		T64	1		T199	1