Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10452389 |
1 |
|
|
T1 |
24284 |
|
T2 |
47900 |
|
T3 |
12057 |
auto[1] |
10452351 |
1 |
|
|
T1 |
24284 |
|
T2 |
47900 |
|
T3 |
12057 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20671308 |
1 |
|
|
T1 |
48360 |
|
T2 |
93928 |
|
T3 |
24024 |
triple_byte_access |
77618 |
1 |
|
|
T1 |
76 |
|
T2 |
620 |
|
T3 |
24 |
halfword_access |
78156 |
1 |
|
|
T1 |
78 |
|
T2 |
632 |
|
T3 |
30 |
byte_access |
77658 |
1 |
|
|
T1 |
54 |
|
T2 |
620 |
|
T3 |
36 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10335673 |
1 |
|
|
T1 |
24180 |
|
T2 |
46964 |
|
T3 |
12012 |
auto[0] |
triple_byte_access |
38809 |
1 |
|
|
T1 |
38 |
|
T2 |
310 |
|
T3 |
12 |
auto[0] |
halfword_access |
39078 |
1 |
|
|
T1 |
39 |
|
T2 |
316 |
|
T3 |
15 |
auto[0] |
byte_access |
38829 |
1 |
|
|
T1 |
27 |
|
T2 |
310 |
|
T3 |
18 |
auto[1] |
word_access |
10335635 |
1 |
|
|
T1 |
24180 |
|
T2 |
46964 |
|
T3 |
12012 |
auto[1] |
triple_byte_access |
38809 |
1 |
|
|
T1 |
38 |
|
T2 |
310 |
|
T3 |
12 |
auto[1] |
halfword_access |
39078 |
1 |
|
|
T1 |
39 |
|
T2 |
316 |
|
T3 |
15 |
auto[1] |
byte_access |
38829 |
1 |
|
|
T1 |
27 |
|
T2 |
310 |
|
T3 |
18 |