Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100605650	1			T2	569849		T3	976		T17	334
all_values[1]	100605650	1			T2	569849		T3	976		T17	334
all_values[2]	100605650	1			T2	569849		T3	976		T17	334

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

493674

1

T2

6

T3

1022

T17

260

auto[1]

301323276

1

T2

170954

T3

1906

T17

742

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300307809

1

T2

169903

T3

2898

T17

960

auto[1]

1509141

1

T2

10512

T3

30

T17

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	182308	1			T2	1		T3	505		T21	236
all_values[0]	auto[0]	auto[1]	1951	1			T2	2		T3	6		T21	2
all_values[0]	auto[1]	auto[0]	99920295	1			T2	566344		T3	461		T17	320
all_values[0]	auto[1]	auto[1]	501096	1			T2	3502		T3	4		T17	14
all_values[1]	auto[0]	auto[0]	130925	1			T3	505		T17	247		T34	2
all_values[1]	auto[0]	auto[1]	1529	1			T3	6		T17	13		T34	1
all_values[1]	auto[1]	auto[0]	99971678	1			T2	566345		T3	461		T17	73
all_values[1]	auto[1]	auto[1]	501518	1			T2	3504		T3	4		T17	1
all_values[2]	auto[0]	auto[0]	175614	1			T2	1		T34	2		T9	9375
all_values[2]	auto[0]	auto[1]	1347	1			T2	2		T34	1		T9	17
all_values[2]	auto[1]	auto[0]	99926989	1			T2	566344		T3	966		T17	320
all_values[2]	auto[1]	auto[1]	501700	1			T2	3502		T3	10		T17	14