Unified Coverage Report :: Group :: kmac_env_pkg::config_masked_cg

Group : kmac_env_pkg::config_masked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_masked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	1	27	96.43
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_masked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
entropy_fast_process	2	0	2	100.00	100	1	1	2
entropy_mode	3	1	2	66.67	100	1	1	0
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_masked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for entropy_fast_process

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170458

1

T2

1135

T3

4

T17

8

auto[1]

169756

1

T2

1202

T3

9

T17

1

---

Summary for Variable entropy_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for entropy_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EntropyModeNone]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[EntropyModeEdn]

169670

1

T2

2337

T3

13

T17

9

auto[EntropyModeSw]

170544

1

T36

374

T9

167

T20

172

---

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	65761	1			T2	481		T3	3		T34	459
auto[Key192]	65047	1			T2	464		T3	4		T34	454
auto[Key256]	79026	1			T2	497		T3	3		T17	9
auto[Key384]	64756	1			T2	458		T3	2		T34	478
auto[Key512]	65624	1			T2	437		T3	1		T34	440

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

309236

1

T2

2337

T3

10

T34

2337

auto[1]

30978

1

T3

3

T17

9

T21

14

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	67219	1			T3	1		T36	374		T21	1
auto[Shake]	238837	1			T2	2337		T3	3		T34	2337
auto[CShake]	34158	1			T3	9		T17	9		T21	14

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170154

1

T2

1206

T3

5

T17

7

auto[1]

170060

1

T2

1131

T3

8

T17

2

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330356

1

T2

2337

T3

12

T17

9

auto[1]

9858

1

T3

1

T21

4

T8

20

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170467

1

T2

1155

T3

5

T17

4

auto[1]

169747

1

T2

1182

T3

8

T17

5

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	138023	1			T2	2337		T3	7		T17	6
auto[L224]	19805	1			T9	2		T20	2		T154	4
auto[L256]	153996	1			T3	5		T17	3		T36	374
auto[L384]	15796	1			T3	1		T21	1		T37	310
auto[L512]	12594	1			T9	1		T20	1		T154	8

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322291

1

T2

2337

T3

12

T17

9

auto[1]

17923

1

T3

1

T21

9

T8

27

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

30978

1

T3

3

T17

9

T21

14

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

34158

1

T3

9

T17

9

T21

14

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

238837

1

T2

2337

T3

3

T34

2337

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

67219

1

T3

1

T36

374

T21

1