Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343582 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T17 |
2 |
auto[1] |
340160 |
1 |
|
|
T2 |
4672 |
|
T3 |
24 |
|
T17 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171365 |
1 |
|
|
T2 |
1193 |
|
T3 |
6 |
|
T17 |
4 |
lower_val |
169141 |
1 |
|
|
T2 |
1144 |
|
T3 |
13 |
|
T34 |
1124 |
zero_val |
1753 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
256660 |
1 |
|
|
T2 |
1210 |
|
T3 |
6 |
|
T17 |
6 |
lower_val |
256838 |
1 |
|
|
T2 |
1106 |
|
T3 |
4 |
|
T17 |
4 |
zero_val |
170244 |
1 |
|
|
T2 |
2358 |
|
T3 |
16 |
|
T17 |
8 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42670 |
1 |
|
|
T36 |
99 |
|
T9 |
32 |
|
T20 |
48 |
higher_val |
higher_val |
auto[1] |
21419 |
1 |
|
|
T2 |
292 |
|
T17 |
2 |
|
T34 |
301 |
higher_val |
lower_val |
auto[0] |
42896 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T36 |
91 |
higher_val |
lower_val |
auto[1] |
21293 |
1 |
|
|
T2 |
290 |
|
T34 |
307 |
|
T37 |
45 |
higher_val |
zero_val |
auto[0] |
73 |
1 |
|
|
T3 |
1 |
|
T21 |
1 |
|
T37 |
1 |
higher_val |
zero_val |
auto[1] |
43014 |
1 |
|
|
T2 |
610 |
|
T3 |
5 |
|
T17 |
2 |
lower_val |
higher_val |
auto[0] |
42320 |
1 |
|
|
T36 |
103 |
|
T9 |
46 |
|
T20 |
41 |
lower_val |
higher_val |
auto[1] |
21199 |
1 |
|
|
T2 |
275 |
|
T3 |
5 |
|
T34 |
290 |
lower_val |
lower_val |
auto[0] |
42441 |
1 |
|
|
T36 |
103 |
|
T9 |
40 |
|
T12 |
1 |
lower_val |
lower_val |
auto[1] |
21072 |
1 |
|
|
T2 |
285 |
|
T3 |
3 |
|
T34 |
267 |
lower_val |
zero_val |
auto[0] |
65 |
1 |
|
|
T192 |
1 |
|
T193 |
1 |
|
T104 |
1 |
lower_val |
zero_val |
auto[1] |
42044 |
1 |
|
|
T2 |
584 |
|
T3 |
5 |
|
T34 |
567 |
zero_val |
higher_val |
auto[0] |
500 |
1 |
|
|
T34 |
1 |
|
T9 |
2 |
|
T80 |
1 |
zero_val |
higher_val |
auto[1] |
122 |
1 |
|
|
T2 |
1 |
|
T9 |
1 |
|
T194 |
2 |
zero_val |
lower_val |
auto[0] |
585 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T36 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T2 |
1 |
|
T34 |
4 |
|
T9 |
1 |
zero_val |
zero_val |
auto[0] |
238 |
1 |
|
|
T3 |
1 |
|
T17 |
1 |
|
T21 |
1 |
zero_val |
zero_val |
auto[1] |
176 |
1 |
|
|
T34 |
4 |
|
T38 |
2 |
|
T9 |
1 |