Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100605650	1			T2	569849		T3	976		T17	334
all_pins[1]	100605650	1			T2	569849		T3	976		T17	334
all_pins[2]	100605650	1			T2	569849		T3	976		T17	334

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301073444	1			T2	170604		T3	2924		T17	988
values[0x1]	743506	1			T2	3502		T3	4		T17	14
transitions[0x0=>0x1]	742011	1			T2	3502		T3	4		T17	14
transitions[0x1=>0x0]	742031	1			T2	3502		T3	4		T17	14

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100104554	1			T2	566347		T3	972		T17	320
all_pins[0]	values[0x1]	501096	1			T2	3502		T3	4		T17	14
all_pins[0]	transitions[0x0=>0x1]	501079	1			T2	3502		T3	4		T17	14
all_pins[0]	transitions[0x1=>0x0]	5734	1			T21	8		T20	28		T22	50
all_pins[1]	values[0x0]	100599899	1			T2	569849		T3	976		T17	334
all_pins[1]	values[0x1]	5751	1			T21	8		T20	28		T22	50
all_pins[1]	transitions[0x0=>0x1]	5651	1			T21	8		T20	28		T22	50
all_pins[1]	transitions[0x1=>0x0]	236559	1			T21	9		T9	8893		T22	1004
all_pins[2]	values[0x0]	100368991	1			T2	569849		T3	976		T17	334
all_pins[2]	values[0x1]	236659	1			T21	9		T9	8893		T22	1004
all_pins[2]	transitions[0x0=>0x1]	235281	1			T21	9		T9	8840		T22	1004
all_pins[2]	transitions[0x1=>0x0]	499738	1			T2	3502		T3	4		T17	14