Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10418549 |
1 |
|
|
T2 |
27235 |
|
T3 |
1396 |
|
T17 |
96 |
auto[1] |
10418540 |
1 |
|
|
T2 |
27235 |
|
T3 |
1396 |
|
T17 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20604177 |
1 |
|
|
T2 |
52796 |
|
T3 |
2782 |
|
T17 |
192 |
triple_byte_access |
77384 |
1 |
|
|
T2 |
558 |
|
T3 |
2 |
|
T34 |
558 |
halfword_access |
78090 |
1 |
|
|
T2 |
558 |
|
T3 |
4 |
|
T34 |
558 |
byte_access |
77438 |
1 |
|
|
T2 |
558 |
|
T3 |
4 |
|
T34 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10302093 |
1 |
|
|
T2 |
26398 |
|
T3 |
1391 |
|
T17 |
96 |
auto[0] |
triple_byte_access |
38692 |
1 |
|
|
T2 |
279 |
|
T3 |
1 |
|
T34 |
279 |
auto[0] |
halfword_access |
39045 |
1 |
|
|
T2 |
279 |
|
T3 |
2 |
|
T34 |
279 |
auto[0] |
byte_access |
38719 |
1 |
|
|
T2 |
279 |
|
T3 |
2 |
|
T34 |
279 |
auto[1] |
word_access |
10302084 |
1 |
|
|
T2 |
26398 |
|
T3 |
1391 |
|
T17 |
96 |
auto[1] |
triple_byte_access |
38692 |
1 |
|
|
T2 |
279 |
|
T3 |
1 |
|
T34 |
279 |
auto[1] |
halfword_access |
39045 |
1 |
|
|
T2 |
279 |
|
T3 |
2 |
|
T34 |
279 |
auto[1] |
byte_access |
38719 |
1 |
|
|
T2 |
279 |
|
T3 |
2 |
|
T34 |
279 |