SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
94.25 | 97.91 | 92.65 | 99.89 | 76.76 | 95.59 | 99.05 | 97.88 |
T1059 | /workspace/coverage/default/6.kmac_error.1286177152 | Jul 13 05:07:20 PM PDT 24 | Jul 13 05:10:50 PM PDT 24 | 8004568996 ps | ||
T1060 | /workspace/coverage/default/29.kmac_smoke.2013281015 | Jul 13 05:16:37 PM PDT 24 | Jul 13 05:17:19 PM PDT 24 | 3786213931 ps | ||
T1061 | /workspace/coverage/default/2.kmac_test_vectors_shake_128.2516966229 | Jul 13 05:05:43 PM PDT 24 | Jul 13 06:35:23 PM PDT 24 | 193349014865 ps | ||
T1062 | /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1136764861 | Jul 13 05:05:18 PM PDT 24 | Jul 13 05:41:08 PM PDT 24 | 119258289536 ps | ||
T1063 | /workspace/coverage/default/31.kmac_key_error.1689235188 | Jul 13 05:17:47 PM PDT 24 | Jul 13 05:17:59 PM PDT 24 | 3347815009 ps | ||
T1064 | /workspace/coverage/default/6.kmac_smoke.3877835870 | Jul 13 05:07:10 PM PDT 24 | Jul 13 05:07:15 PM PDT 24 | 134994613 ps | ||
T1065 | /workspace/coverage/default/18.kmac_app.3778719448 | Jul 13 05:12:52 PM PDT 24 | Jul 13 05:13:48 PM PDT 24 | 3663489735 ps | ||
T1066 | /workspace/coverage/default/41.kmac_key_error.809136037 | Jul 13 05:21:34 PM PDT 24 | Jul 13 05:21:42 PM PDT 24 | 910431814 ps | ||
T1067 | /workspace/coverage/default/16.kmac_key_error.2526052302 | Jul 13 05:12:00 PM PDT 24 | Jul 13 05:12:03 PM PDT 24 | 328254335 ps | ||
T1068 | /workspace/coverage/default/24.kmac_test_vectors_shake_256.1469926025 | Jul 13 05:14:58 PM PDT 24 | Jul 13 06:44:24 PM PDT 24 | 2162984953674 ps | ||
T1069 | /workspace/coverage/default/26.kmac_burst_write.3746616903 | Jul 13 05:15:30 PM PDT 24 | Jul 13 05:23:48 PM PDT 24 | 5135511880 ps | ||
T1070 | /workspace/coverage/default/34.kmac_entropy_refresh.3278431968 | Jul 13 05:18:56 PM PDT 24 | Jul 13 05:23:46 PM PDT 24 | 11318592371 ps | ||
T1071 | /workspace/coverage/default/45.kmac_burst_write.1825322996 | Jul 13 05:22:54 PM PDT 24 | Jul 13 05:26:26 PM PDT 24 | 8889386037 ps | ||
T1072 | /workspace/coverage/default/42.kmac_long_msg_and_output.3885625908 | Jul 13 05:21:44 PM PDT 24 | Jul 13 06:03:34 PM PDT 24 | 269295477519 ps | ||
T1073 | /workspace/coverage/default/27.kmac_test_vectors_shake_128.2987597175 | Jul 13 05:16:05 PM PDT 24 | Jul 13 06:36:51 PM PDT 24 | 122929892685 ps | ||
T1074 | /workspace/coverage/default/21.kmac_burst_write.4101480539 | Jul 13 05:13:56 PM PDT 24 | Jul 13 05:18:23 PM PDT 24 | 2831629606 ps | ||
T1075 | /workspace/coverage/default/9.kmac_entropy_mode_error.3972657517 | Jul 13 05:08:56 PM PDT 24 | Jul 13 05:08:58 PM PDT 24 | 36124358 ps | ||
T1076 | /workspace/coverage/default/29.kmac_error.1415603404 | Jul 13 05:17:07 PM PDT 24 | Jul 13 05:18:37 PM PDT 24 | 6693995249 ps | ||
T1077 | /workspace/coverage/default/10.kmac_test_vectors_shake_256.1589803418 | Jul 13 05:09:05 PM PDT 24 | Jul 13 06:20:18 PM PDT 24 | 298339124170 ps | ||
T88 | /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1274555899 | Jul 13 04:59:22 PM PDT 24 | Jul 13 04:59:25 PM PDT 24 | 265067645 ps | ||
T168 | /workspace/coverage/cover_reg_top/15.kmac_csr_rw.877452297 | Jul 13 05:01:08 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 99469204 ps | ||
T1078 | /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2113558682 | Jul 13 05:00:21 PM PDT 24 | Jul 13 05:00:22 PM PDT 24 | 198942467 ps | ||
T191 | /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1741566516 | Jul 13 04:59:57 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 428658271 ps | ||
T100 | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1963868049 | Jul 13 04:59:58 PM PDT 24 | Jul 13 04:59:59 PM PDT 24 | 182404109 ps | ||
T157 | /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4188822496 | Jul 13 04:59:22 PM PDT 24 | Jul 13 04:59:23 PM PDT 24 | 31431674 ps | ||
T131 | /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2512842714 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:49 PM PDT 24 | 149283309 ps | ||
T1079 | /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2371796036 | Jul 13 05:00:31 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 50081208 ps | ||
T138 | /workspace/coverage/cover_reg_top/26.kmac_intr_test.2144882871 | Jul 13 05:01:33 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 86024684 ps | ||
T85 | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2310066718 | Jul 13 05:00:50 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 84560966 ps | ||
T139 | /workspace/coverage/cover_reg_top/2.kmac_intr_test.1778396849 | Jul 13 04:59:49 PM PDT 24 | Jul 13 04:59:50 PM PDT 24 | 15714344 ps | ||
T137 | /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2712246974 | Jul 13 04:59:50 PM PDT 24 | Jul 13 04:59:53 PM PDT 24 | 87205286 ps | ||
T140 | /workspace/coverage/cover_reg_top/8.kmac_intr_test.538695357 | Jul 13 05:00:36 PM PDT 24 | Jul 13 05:00:38 PM PDT 24 | 37323056 ps | ||
T133 | /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.4130394060 | Jul 13 04:59:40 PM PDT 24 | Jul 13 04:59:45 PM PDT 24 | 893653106 ps | ||
T158 | /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1706502026 | Jul 13 04:59:44 PM PDT 24 | Jul 13 04:59:46 PM PDT 24 | 21530101 ps | ||
T134 | /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2186165047 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 1356919578 ps | ||
T86 | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3449507836 | Jul 13 05:00:07 PM PDT 24 | Jul 13 05:00:09 PM PDT 24 | 28762228 ps | ||
T87 | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1166778938 | Jul 13 05:00:22 PM PDT 24 | Jul 13 05:00:24 PM PDT 24 | 73989731 ps | ||
T101 | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2233600483 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 222661535 ps | ||
T1080 | /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1549463666 | Jul 13 05:00:51 PM PDT 24 | Jul 13 05:00:54 PM PDT 24 | 471490919 ps | ||
T145 | /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3354609547 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:53 PM PDT 24 | 467424120 ps | ||
T173 | /workspace/coverage/cover_reg_top/41.kmac_intr_test.2931466664 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 44492337 ps | ||
T94 | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.422011070 | Jul 13 05:00:31 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 115275101 ps | ||
T89 | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2906170915 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 207753499 ps | ||
T1081 | /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3062570314 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 28773108 ps | ||
T178 | /workspace/coverage/cover_reg_top/30.kmac_intr_test.1568616807 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 29253498 ps | ||
T1082 | /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3459623763 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:31 PM PDT 24 | 15634989 ps | ||
T90 | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4199509268 | Jul 13 05:00:34 PM PDT 24 | Jul 13 05:00:37 PM PDT 24 | 294203502 ps | ||
T151 | /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1564860070 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:02 PM PDT 24 | 96393497 ps | ||
T174 | /workspace/coverage/cover_reg_top/9.kmac_intr_test.1296775251 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:48 PM PDT 24 | 15299403 ps | ||
T102 | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2754729441 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:55 PM PDT 24 | 56426574 ps | ||
T1083 | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3867940426 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 185585292 ps | ||
T143 | /workspace/coverage/cover_reg_top/6.kmac_tl_errors.830882383 | Jul 13 05:00:28 PM PDT 24 | Jul 13 05:00:32 PM PDT 24 | 46732725 ps | ||
T144 | /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2417842344 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 80333456 ps | ||
T176 | /workspace/coverage/cover_reg_top/25.kmac_intr_test.2284000421 | Jul 13 05:01:28 PM PDT 24 | Jul 13 05:01:30 PM PDT 24 | 16500590 ps | ||
T1084 | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.586580130 | Jul 13 04:59:14 PM PDT 24 | Jul 13 04:59:16 PM PDT 24 | 35691009 ps | ||
T175 | /workspace/coverage/cover_reg_top/39.kmac_intr_test.3751204119 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:31 PM PDT 24 | 11651392 ps | ||
T1085 | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.350802755 | Jul 13 04:59:43 PM PDT 24 | Jul 13 04:59:44 PM PDT 24 | 125106790 ps | ||
T177 | /workspace/coverage/cover_reg_top/1.kmac_intr_test.3484235025 | Jul 13 04:59:39 PM PDT 24 | Jul 13 04:59:40 PM PDT 24 | 12311570 ps | ||
T1086 | /workspace/coverage/cover_reg_top/45.kmac_intr_test.3299951053 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:31 PM PDT 24 | 15299193 ps | ||
T166 | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.837320750 | Jul 13 05:00:37 PM PDT 24 | Jul 13 05:00:39 PM PDT 24 | 33289772 ps | ||
T1087 | /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2114140247 | Jul 13 04:59:58 PM PDT 24 | Jul 13 05:00:08 PM PDT 24 | 773152771 ps | ||
T91 | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1033181516 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:15 PM PDT 24 | 146495861 ps | ||
T146 | /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2258466173 | Jul 13 05:00:21 PM PDT 24 | Jul 13 05:00:24 PM PDT 24 | 114877516 ps | ||
T142 | /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1450712046 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:56 PM PDT 24 | 183271096 ps | ||
T1088 | /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.325938612 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:15 PM PDT 24 | 27508516 ps | ||
T92 | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3146531772 | Jul 13 05:00:29 PM PDT 24 | Jul 13 05:00:31 PM PDT 24 | 110313649 ps | ||
T1089 | /workspace/coverage/cover_reg_top/31.kmac_intr_test.1646710626 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:31 PM PDT 24 | 44062419 ps | ||
T1090 | /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2619166050 | Jul 13 04:59:29 PM PDT 24 | Jul 13 04:59:31 PM PDT 24 | 34937944 ps | ||
T1091 | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1085766096 | Jul 13 05:00:37 PM PDT 24 | Jul 13 05:00:38 PM PDT 24 | 51038088 ps | ||
T1092 | /workspace/coverage/cover_reg_top/46.kmac_intr_test.2920762208 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 36042669 ps | ||
T1093 | /workspace/coverage/cover_reg_top/21.kmac_intr_test.3748423059 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 69622053 ps | ||
T97 | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.599899068 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:00 PM PDT 24 | 51244354 ps | ||
T1094 | /workspace/coverage/cover_reg_top/33.kmac_intr_test.2441364212 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 16981615 ps | ||
T1095 | /workspace/coverage/cover_reg_top/4.kmac_intr_test.726164572 | Jul 13 05:00:12 PM PDT 24 | Jul 13 05:00:13 PM PDT 24 | 57255794 ps | ||
T1096 | /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1159962062 | Jul 13 05:00:39 PM PDT 24 | Jul 13 05:00:41 PM PDT 24 | 193571766 ps | ||
T152 | /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3541487166 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:16 PM PDT 24 | 82743131 ps | ||
T1097 | /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1382241063 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 42823910 ps | ||
T1098 | /workspace/coverage/cover_reg_top/14.kmac_csr_rw.312084676 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:00 PM PDT 24 | 29645259 ps | ||
T159 | /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2793039354 | Jul 13 05:00:00 PM PDT 24 | Jul 13 05:00:02 PM PDT 24 | 54590239 ps | ||
T132 | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1319138900 | Jul 13 05:01:21 PM PDT 24 | Jul 13 05:01:24 PM PDT 24 | 44705554 ps | ||
T1099 | /workspace/coverage/cover_reg_top/16.kmac_intr_test.984069076 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:15 PM PDT 24 | 15200238 ps | ||
T1100 | /workspace/coverage/cover_reg_top/36.kmac_intr_test.1652893855 | Jul 13 05:01:31 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 21736192 ps | ||
T167 | /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2401257094 | Jul 13 05:00:39 PM PDT 24 | Jul 13 05:00:41 PM PDT 24 | 33318422 ps | ||
T1101 | /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3198944782 | Jul 13 05:00:04 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 113111735 ps | ||
T153 | /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.488925628 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 41473830 ps | ||
T1102 | /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.411865228 | Jul 13 05:00:05 PM PDT 24 | Jul 13 05:00:07 PM PDT 24 | 162803434 ps | ||
T160 | /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2000471456 | Jul 13 04:59:37 PM PDT 24 | Jul 13 04:59:39 PM PDT 24 | 73559696 ps | ||
T141 | /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3751775714 | Jul 13 05:00:36 PM PDT 24 | Jul 13 05:00:38 PM PDT 24 | 46862205 ps | ||
T1103 | /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4014284962 | Jul 13 04:59:43 PM PDT 24 | Jul 13 04:59:44 PM PDT 24 | 16579721 ps | ||
T1104 | /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.838749475 | Jul 13 05:00:50 PM PDT 24 | Jul 13 05:00:54 PM PDT 24 | 226044146 ps | ||
T1105 | /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1108368220 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 321858033 ps | ||
T1106 | /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2146535842 | Jul 13 05:00:04 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 26750505 ps | ||
T93 | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3636780007 | Jul 13 05:00:36 PM PDT 24 | Jul 13 05:00:39 PM PDT 24 | 79227944 ps | ||
T1107 | /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1561584187 | Jul 13 05:00:07 PM PDT 24 | Jul 13 05:00:17 PM PDT 24 | 2018083936 ps | ||
T1108 | /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1802606532 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 42423766 ps | ||
T1109 | /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3048337778 | Jul 13 05:00:15 PM PDT 24 | Jul 13 05:00:25 PM PDT 24 | 494627085 ps | ||
T1110 | /workspace/coverage/cover_reg_top/10.kmac_csr_rw.125957537 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 69601964 ps | ||
T1111 | /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1935795774 | Jul 13 05:00:10 PM PDT 24 | Jul 13 05:00:12 PM PDT 24 | 90235543 ps | ||
T1112 | /workspace/coverage/cover_reg_top/14.kmac_intr_test.2762563942 | Jul 13 05:01:01 PM PDT 24 | Jul 13 05:01:02 PM PDT 24 | 15155201 ps | ||
T186 | /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.49760462 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:53 PM PDT 24 | 374800565 ps | ||
T1113 | /workspace/coverage/cover_reg_top/11.kmac_intr_test.1230293382 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 14687482 ps | ||
T1114 | /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1530170323 | Jul 13 04:59:38 PM PDT 24 | Jul 13 04:59:39 PM PDT 24 | 24949151 ps | ||
T187 | /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3221384325 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:57 PM PDT 24 | 145465314 ps | ||
T1115 | /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.909886244 | Jul 13 04:59:44 PM PDT 24 | Jul 13 04:59:46 PM PDT 24 | 266194284 ps | ||
T1116 | /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.160621608 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:01 PM PDT 24 | 175439507 ps | ||
T1117 | /workspace/coverage/cover_reg_top/38.kmac_intr_test.288617576 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 11960658 ps | ||
T1118 | /workspace/coverage/cover_reg_top/18.kmac_intr_test.2422878852 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 17806166 ps | ||
T1119 | /workspace/coverage/cover_reg_top/15.kmac_intr_test.4169171597 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 108948293 ps | ||
T1120 | /workspace/coverage/cover_reg_top/34.kmac_intr_test.3054291936 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 82359988 ps | ||
T1121 | /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2203969606 | Jul 13 05:00:12 PM PDT 24 | Jul 13 05:00:28 PM PDT 24 | 292818939 ps | ||
T1122 | /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.982177103 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 27421278 ps | ||
T95 | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3288904979 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 75901921 ps | ||
T1123 | /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1365085070 | Jul 13 05:00:21 PM PDT 24 | Jul 13 05:00:23 PM PDT 24 | 48207175 ps | ||
T98 | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2361693259 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:49 PM PDT 24 | 71740657 ps | ||
T1124 | /workspace/coverage/cover_reg_top/0.kmac_intr_test.3902975703 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:24 PM PDT 24 | 80779509 ps | ||
T1125 | /workspace/coverage/cover_reg_top/44.kmac_intr_test.3901572560 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 13694154 ps | ||
T136 | /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3588685719 | Jul 13 05:01:16 PM PDT 24 | Jul 13 05:01:19 PM PDT 24 | 144720345 ps | ||
T1126 | /workspace/coverage/cover_reg_top/23.kmac_intr_test.3064502559 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:31 PM PDT 24 | 17987616 ps | ||
T1127 | /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1149333164 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 59156640 ps | ||
T1128 | /workspace/coverage/cover_reg_top/0.kmac_csr_rw.880162022 | Jul 13 04:59:22 PM PDT 24 | Jul 13 04:59:23 PM PDT 24 | 26476782 ps | ||
T1129 | /workspace/coverage/cover_reg_top/11.kmac_csr_rw.506468324 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 66171152 ps | ||
T1130 | /workspace/coverage/cover_reg_top/28.kmac_intr_test.1122327684 | Jul 13 05:01:31 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 39253174 ps | ||
T1131 | /workspace/coverage/cover_reg_top/40.kmac_intr_test.1260217775 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 28024499 ps | ||
T1132 | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2652056578 | Jul 13 05:01:01 PM PDT 24 | Jul 13 05:01:03 PM PDT 24 | 237521100 ps | ||
T188 | /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.4174110271 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 126746702 ps | ||
T1133 | /workspace/coverage/cover_reg_top/4.kmac_tl_errors.577319275 | Jul 13 05:00:05 PM PDT 24 | Jul 13 05:00:07 PM PDT 24 | 246374867 ps | ||
T1134 | /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3906880817 | Jul 13 04:59:43 PM PDT 24 | Jul 13 05:00:03 PM PDT 24 | 3917762598 ps | ||
T1135 | /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.8513530 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:19 PM PDT 24 | 104850411 ps | ||
T1136 | /workspace/coverage/cover_reg_top/0.kmac_mem_walk.4048154131 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:24 PM PDT 24 | 12737161 ps | ||
T1137 | /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3591146938 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:25 PM PDT 24 | 86942117 ps | ||
T1138 | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3268128236 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 269935273 ps | ||
T1139 | /workspace/coverage/cover_reg_top/17.kmac_intr_test.1355218760 | Jul 13 05:01:16 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 18425788 ps | ||
T1140 | /workspace/coverage/cover_reg_top/19.kmac_csr_rw.989376507 | Jul 13 05:01:22 PM PDT 24 | Jul 13 05:01:24 PM PDT 24 | 34685886 ps | ||
T1141 | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3532174819 | Jul 13 05:01:14 PM PDT 24 | Jul 13 05:01:16 PM PDT 24 | 105445204 ps | ||
T1142 | /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1075439640 | Jul 13 05:00:50 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 85927870 ps | ||
T1143 | /workspace/coverage/cover_reg_top/35.kmac_intr_test.2937621199 | Jul 13 05:01:33 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 102582744 ps | ||
T1144 | /workspace/coverage/cover_reg_top/10.kmac_intr_test.237800952 | Jul 13 05:00:50 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 13936709 ps | ||
T1145 | /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1196244939 | Jul 13 04:59:56 PM PDT 24 | Jul 13 04:59:57 PM PDT 24 | 29142768 ps | ||
T1146 | /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4080718010 | Jul 13 04:59:24 PM PDT 24 | Jul 13 04:59:26 PM PDT 24 | 44031408 ps | ||
T1147 | /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1695634720 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:33 PM PDT 24 | 396377662 ps | ||
T1148 | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3841567027 | Jul 13 04:59:44 PM PDT 24 | Jul 13 04:59:46 PM PDT 24 | 33264223 ps | ||
T96 | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.413526445 | Jul 13 05:01:06 PM PDT 24 | Jul 13 05:01:07 PM PDT 24 | 18966222 ps | ||
T1149 | /workspace/coverage/cover_reg_top/24.kmac_intr_test.2412713618 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 23060549 ps | ||
T1150 | /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.495634602 | Jul 13 05:00:29 PM PDT 24 | Jul 13 05:00:32 PM PDT 24 | 115602719 ps | ||
T189 | /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4162600859 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:12 PM PDT 24 | 186443945 ps | ||
T1151 | /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3256437649 | Jul 13 05:01:06 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 164688618 ps | ||
T1152 | /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3717472535 | Jul 13 04:59:57 PM PDT 24 | Jul 13 04:59:59 PM PDT 24 | 36196831 ps | ||
T1153 | /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1761277283 | Jul 13 05:00:51 PM PDT 24 | Jul 13 05:00:53 PM PDT 24 | 23456613 ps | ||
T1154 | /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1731766840 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 149841163 ps | ||
T1155 | /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3204821141 | Jul 13 05:00:21 PM PDT 24 | Jul 13 05:00:24 PM PDT 24 | 40190550 ps | ||
T1156 | /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2511390855 | Jul 13 05:00:31 PM PDT 24 | Jul 13 05:00:33 PM PDT 24 | 22550064 ps | ||
T184 | /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3254721686 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:19 PM PDT 24 | 192225370 ps | ||
T1157 | /workspace/coverage/cover_reg_top/32.kmac_intr_test.3919772440 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:31 PM PDT 24 | 25960340 ps | ||
T1158 | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1126336367 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 45551415 ps | ||
T1159 | /workspace/coverage/cover_reg_top/47.kmac_intr_test.3372374179 | Jul 13 05:01:33 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 39229118 ps | ||
T1160 | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3288336911 | Jul 13 05:00:04 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 63276635 ps | ||
T1161 | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.468358422 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:53 PM PDT 24 | 35310744 ps | ||
T1162 | /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2690742973 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:24 PM PDT 24 | 60937588 ps | ||
T1163 | /workspace/coverage/cover_reg_top/42.kmac_intr_test.3803782200 | Jul 13 05:01:32 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 24782487 ps | ||
T1164 | /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1289351720 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:03 PM PDT 24 | 38641948 ps | ||
T1165 | /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1122803439 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 82748905 ps | ||
T1166 | /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.871211256 | Jul 13 04:59:43 PM PDT 24 | Jul 13 04:59:49 PM PDT 24 | 1491041018 ps | ||
T1167 | /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1518211263 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:18 PM PDT 24 | 150278045 ps | ||
T185 | /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3179268374 | Jul 13 05:01:23 PM PDT 24 | Jul 13 05:01:28 PM PDT 24 | 885595682 ps | ||
T190 | /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1837121577 | Jul 13 05:00:06 PM PDT 24 | Jul 13 05:00:10 PM PDT 24 | 111640306 ps | ||
T1168 | /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2350910040 | Jul 13 05:01:09 PM PDT 24 | Jul 13 05:01:12 PM PDT 24 | 230121363 ps | ||
T1169 | /workspace/coverage/cover_reg_top/5.kmac_intr_test.1903569174 | Jul 13 05:00:21 PM PDT 24 | Jul 13 05:00:22 PM PDT 24 | 23579605 ps | ||
T1170 | /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.304533606 | Jul 13 05:00:31 PM PDT 24 | Jul 13 05:00:34 PM PDT 24 | 88102085 ps | ||
T1171 | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.4251390874 | Jul 13 05:01:09 PM PDT 24 | Jul 13 05:01:11 PM PDT 24 | 96601243 ps | ||
T1172 | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.906769262 | Jul 13 04:59:15 PM PDT 24 | Jul 13 04:59:18 PM PDT 24 | 121073539 ps | ||
T99 | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.451470133 | Jul 13 05:00:47 PM PDT 24 | Jul 13 05:00:50 PM PDT 24 | 98802663 ps | ||
T1173 | /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3440753693 | Jul 13 05:00:06 PM PDT 24 | Jul 13 05:00:08 PM PDT 24 | 173427103 ps | ||
T1174 | /workspace/coverage/cover_reg_top/43.kmac_intr_test.2854498871 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 27831931 ps | ||
T1175 | /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4202786673 | Jul 13 05:00:22 PM PDT 24 | Jul 13 05:00:23 PM PDT 24 | 17140946 ps | ||
T1176 | /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4087976308 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:18 PM PDT 24 | 115382686 ps | ||
T1177 | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.295463432 | Jul 13 05:00:15 PM PDT 24 | Jul 13 05:00:17 PM PDT 24 | 27319868 ps | ||
T1178 | /workspace/coverage/cover_reg_top/0.kmac_tl_errors.900121105 | Jul 13 04:59:23 PM PDT 24 | Jul 13 04:59:26 PM PDT 24 | 203055499 ps | ||
T1179 | /workspace/coverage/cover_reg_top/19.kmac_intr_test.2242069533 | Jul 13 05:01:23 PM PDT 24 | Jul 13 05:01:24 PM PDT 24 | 16066755 ps | ||
T1180 | /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2284673709 | Jul 13 05:01:23 PM PDT 24 | Jul 13 05:01:25 PM PDT 24 | 28443898 ps | ||
T1181 | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1423912660 | Jul 13 04:59:58 PM PDT 24 | Jul 13 05:00:01 PM PDT 24 | 497063571 ps | ||
T1182 | /workspace/coverage/cover_reg_top/13.kmac_intr_test.369030929 | Jul 13 05:01:01 PM PDT 24 | Jul 13 05:01:02 PM PDT 24 | 33319509 ps | ||
T1183 | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.262368407 | Jul 13 04:59:30 PM PDT 24 | Jul 13 04:59:31 PM PDT 24 | 80866020 ps | ||
T1184 | /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3872918333 | Jul 13 04:59:58 PM PDT 24 | Jul 13 05:00:01 PM PDT 24 | 1255436464 ps | ||
T1185 | /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3968565161 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 108109063 ps | ||
T1186 | /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2378125368 | Jul 13 05:00:59 PM PDT 24 | Jul 13 05:01:02 PM PDT 24 | 68917196 ps | ||
T1187 | /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.487994613 | Jul 13 04:59:37 PM PDT 24 | Jul 13 04:59:39 PM PDT 24 | 56112655 ps | ||
T1188 | /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2027756824 | Jul 13 05:00:11 PM PDT 24 | Jul 13 05:00:13 PM PDT 24 | 28058755 ps | ||
T1189 | /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2343374215 | Jul 13 05:00:05 PM PDT 24 | Jul 13 05:00:10 PM PDT 24 | 266285679 ps | ||
T1190 | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.545518601 | Jul 13 04:59:29 PM PDT 24 | Jul 13 04:59:31 PM PDT 24 | 157334085 ps | ||
T1191 | /workspace/coverage/cover_reg_top/22.kmac_intr_test.2410502707 | Jul 13 05:01:32 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 42984830 ps | ||
T1192 | /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.810400983 | Jul 13 04:59:49 PM PDT 24 | Jul 13 04:59:50 PM PDT 24 | 57727758 ps | ||
T1193 | /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4126385457 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 135131753 ps | ||
T1194 | /workspace/coverage/cover_reg_top/20.kmac_intr_test.3972112914 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 14418492 ps | ||
T1195 | /workspace/coverage/cover_reg_top/6.kmac_intr_test.1902110662 | Jul 13 05:00:30 PM PDT 24 | Jul 13 05:00:31 PM PDT 24 | 11819794 ps | ||
T1196 | /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2500489219 | Jul 13 05:00:49 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 577632927 ps | ||
T1197 | /workspace/coverage/cover_reg_top/16.kmac_csr_rw.170917621 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 28086279 ps | ||
T161 | /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2116342445 | Jul 13 05:00:04 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 22326194 ps | ||
T1198 | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1615839728 | Jul 13 05:00:32 PM PDT 24 | Jul 13 05:00:36 PM PDT 24 | 439713882 ps | ||
T1199 | /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2969619452 | Jul 13 05:01:09 PM PDT 24 | Jul 13 05:01:11 PM PDT 24 | 808309747 ps | ||
T1200 | /workspace/coverage/cover_reg_top/1.kmac_tl_errors.531402778 | Jul 13 04:59:38 PM PDT 24 | Jul 13 04:59:39 PM PDT 24 | 271855932 ps | ||
T1201 | /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1064281824 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 42109771 ps | ||
T1202 | /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2606441211 | Jul 13 05:00:05 PM PDT 24 | Jul 13 05:00:06 PM PDT 24 | 10842953 ps | ||
T1203 | /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1020017489 | Jul 13 05:00:48 PM PDT 24 | Jul 13 05:00:51 PM PDT 24 | 415268496 ps | ||
T1204 | /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2435438786 | Jul 13 05:01:09 PM PDT 24 | Jul 13 05:01:12 PM PDT 24 | 321091018 ps | ||
T1205 | /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1158257171 | Jul 13 04:59:43 PM PDT 24 | Jul 13 04:59:46 PM PDT 24 | 36319683 ps | ||
T1206 | /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3350261587 | Jul 13 05:00:15 PM PDT 24 | Jul 13 05:00:17 PM PDT 24 | 131879386 ps | ||
T1207 | /workspace/coverage/cover_reg_top/7.kmac_csr_rw.385729087 | Jul 13 05:00:28 PM PDT 24 | Jul 13 05:00:29 PM PDT 24 | 23816873 ps | ||
T1208 | /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1102738859 | Jul 13 05:00:04 PM PDT 24 | Jul 13 05:00:05 PM PDT 24 | 70968798 ps | ||
T1209 | /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3351243669 | Jul 13 05:00:14 PM PDT 24 | Jul 13 05:00:15 PM PDT 24 | 34082565 ps | ||
T1210 | /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.224271468 | Jul 13 04:59:50 PM PDT 24 | Jul 13 04:59:54 PM PDT 24 | 333125331 ps | ||
T1211 | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1245238332 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:55 PM PDT 24 | 103620165 ps | ||
T1212 | /workspace/coverage/cover_reg_top/27.kmac_intr_test.1350987547 | Jul 13 05:01:30 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 40749140 ps | ||
T1213 | /workspace/coverage/cover_reg_top/49.kmac_intr_test.4256324847 | Jul 13 05:01:36 PM PDT 24 | Jul 13 05:01:37 PM PDT 24 | 52972099 ps | ||
T1214 | /workspace/coverage/cover_reg_top/3.kmac_intr_test.332436920 | Jul 13 05:00:06 PM PDT 24 | Jul 13 05:00:07 PM PDT 24 | 164735901 ps | ||
T1215 | /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2079983390 | Jul 13 05:00:05 PM PDT 24 | Jul 13 05:00:13 PM PDT 24 | 518564891 ps | ||
T1216 | /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2277916531 | Jul 13 04:59:24 PM PDT 24 | Jul 13 04:59:33 PM PDT 24 | 164666653 ps | ||
T1217 | /workspace/coverage/cover_reg_top/37.kmac_intr_test.607241834 | Jul 13 05:01:31 PM PDT 24 | Jul 13 05:01:33 PM PDT 24 | 46156440 ps | ||
T1218 | /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1800474692 | Jul 13 05:01:28 PM PDT 24 | Jul 13 05:01:30 PM PDT 24 | 116199139 ps | ||
T1219 | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3590112965 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 87694340 ps | ||
T1220 | /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1344832185 | Jul 13 05:01:17 PM PDT 24 | Jul 13 05:01:19 PM PDT 24 | 127129473 ps | ||
T1221 | /workspace/coverage/cover_reg_top/12.kmac_intr_test.2286824911 | Jul 13 05:00:51 PM PDT 24 | Jul 13 05:00:52 PM PDT 24 | 50407399 ps | ||
T1222 | /workspace/coverage/cover_reg_top/29.kmac_intr_test.4217221933 | Jul 13 05:01:32 PM PDT 24 | Jul 13 05:01:34 PM PDT 24 | 14749765 ps | ||
T1223 | /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3734986257 | Jul 13 05:00:52 PM PDT 24 | Jul 13 05:00:54 PM PDT 24 | 56066954 ps | ||
T1224 | /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1206086533 | Jul 13 05:01:07 PM PDT 24 | Jul 13 05:01:09 PM PDT 24 | 220851538 ps | ||
T1225 | /workspace/coverage/cover_reg_top/13.kmac_csr_rw.414548333 | Jul 13 05:00:58 PM PDT 24 | Jul 13 05:00:59 PM PDT 24 | 39520948 ps | ||
T1226 | /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1990668485 | Jul 13 05:00:37 PM PDT 24 | Jul 13 05:00:40 PM PDT 24 | 385074548 ps | ||
T1227 | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.987519537 | Jul 13 05:01:06 PM PDT 24 | Jul 13 05:01:08 PM PDT 24 | 104454547 ps | ||
T1228 | /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4125649925 | Jul 13 05:01:15 PM PDT 24 | Jul 13 05:01:17 PM PDT 24 | 75341186 ps | ||
T1229 | /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1198254301 | Jul 13 05:01:29 PM PDT 24 | Jul 13 05:01:32 PM PDT 24 | 162371205 ps | ||
T1230 | /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1750077096 | Jul 13 05:00:36 PM PDT 24 | Jul 13 05:00:41 PM PDT 24 | 135400434 ps | ||
T1231 | /workspace/coverage/cover_reg_top/48.kmac_intr_test.1994646158 | Jul 13 05:01:37 PM PDT 24 | Jul 13 05:01:38 PM PDT 24 | 15270796 ps | ||
T1232 | /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4068006486 | Jul 13 05:01:17 PM PDT 24 | Jul 13 05:01:20 PM PDT 24 | 29877980 ps | ||
T1233 | /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3927630427 | Jul 13 04:59:59 PM PDT 24 | Jul 13 05:00:00 PM PDT 24 | 17536479 ps | ||
T1234 | /workspace/coverage/cover_reg_top/7.kmac_intr_test.3841117273 | Jul 13 05:00:31 PM PDT 24 | Jul 13 05:00:32 PM PDT 24 | 55410897 ps |
Test location | /workspace/coverage/default/10.kmac_stress_all.3167883401 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 567269704 ps |
CPU time | 21.08 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:09:55 PM PDT 24 |
Peak memory | 233360 kb |
Host | smart-183d70da-98d3-4e71-b38a-5774389979c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3167883401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3167883401 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_stress_all/latest |
Test location | /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.2992822750 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 16088476551 ps |
CPU time | 291.99 seconds |
Started | Jul 13 05:08:28 PM PDT 24 |
Finished | Jul 13 05:13:21 PM PDT 24 |
Peak memory | 259100 kb |
Host | smart-1ba7955d-1b40-4263-9628-3f40ee5f39a6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2992822750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.2992822750 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.4130394060 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 893653106 ps |
CPU time | 5.24 seconds |
Started | Jul 13 04:59:40 PM PDT 24 |
Finished | Jul 13 04:59:45 PM PDT 24 |
Peak memory | 216092 kb |
Host | smart-ec0a2ea2-b7f5-45be-9122-aa9e97fb6ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130394060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.41303 94060 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/3.kmac_stress_all.725882208 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 99392128663 ps |
CPU time | 1276.32 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:27:29 PM PDT 24 |
Peak memory | 368232 kb |
Host | smart-39755be9-67cf-496d-8526-55a3b9e49909 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=725882208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.725882208 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_stress_all/latest |
Test location | /workspace/coverage/default/23.kmac_lc_escalation.1659748760 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 49616843 ps |
CPU time | 1.51 seconds |
Started | Jul 13 05:14:40 PM PDT 24 |
Finished | Jul 13 05:14:42 PM PDT 24 |
Peak memory | 226580 kb |
Host | smart-e768f18b-4783-47d1-b702-0484110b2bf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659748760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1659748760 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/23.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/4.kmac_sec_cm.2620940595 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 66078134494 ps |
CPU time | 120.25 seconds |
Started | Jul 13 05:06:34 PM PDT 24 |
Finished | Jul 13 05:08:35 PM PDT 24 |
Peak memory | 255884 kb |
Host | smart-f161bd4c-251a-4216-8f21-0dce08912dd4 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620940595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2620940595 +enable_maski ng=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_sec_cm/latest |
Test location | /workspace/coverage/default/13.kmac_key_error.3227698521 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 214418460 ps |
CPU time | 2.4 seconds |
Started | Jul 13 05:10:32 PM PDT 24 |
Finished | Jul 13 05:10:35 PM PDT 24 |
Peak memory | 222496 kb |
Host | smart-74ba3cc8-e877-4ee1-9fbc-da360de378d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227698521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3227698521 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_key_error/latest |
Test location | /workspace/coverage/default/6.kmac_lc_escalation.2286674687 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 95388992 ps |
CPU time | 1.59 seconds |
Started | Jul 13 05:07:30 PM PDT 24 |
Finished | Jul 13 05:07:32 PM PDT 24 |
Peak memory | 226544 kb |
Host | smart-acd8a369-e409-4bd7-83bd-4e38bcff1eb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286674687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2286674687 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/6.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/43.kmac_error.2928408266 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 5602660434 ps |
CPU time | 456.06 seconds |
Started | Jul 13 05:22:29 PM PDT 24 |
Finished | Jul 13 05:30:05 PM PDT 24 |
Peak memory | 267856 kb |
Host | smart-1250b953-73c9-4edc-bf9a-92a5a439ff37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928408266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2928408266 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_error/latest |
Test location | /workspace/coverage/default/4.kmac_entropy_ready_error.507307130 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 32829622601 ps |
CPU time | 62.47 seconds |
Started | Jul 13 05:06:35 PM PDT 24 |
Finished | Jul 13 05:07:38 PM PDT 24 |
Peak memory | 226676 kb |
Host | smart-f048bd30-9416-4dd8-857f-dfb36bdeb5b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507307130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.507307130 +enable_maskin g=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_intr_test.1778396849 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 15714344 ps |
CPU time | 0.78 seconds |
Started | Jul 13 04:59:49 PM PDT 24 |
Finished | Jul 13 04:59:50 PM PDT 24 |
Peak memory | 215708 kb |
Host | smart-e79213a5-f4a9-4fe6-a917-04c99d4de248 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778396849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1778396849 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_intr_test/latest |
Test location | /workspace/coverage/default/44.kmac_lc_escalation.1062902289 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 74951467 ps |
CPU time | 1.32 seconds |
Started | Jul 13 05:22:45 PM PDT 24 |
Finished | Jul 13 05:22:46 PM PDT 24 |
Peak memory | 226416 kb |
Host | smart-98e42fc8-1387-4ca2-97bd-00102fef03a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062902289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1062902289 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/44.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/1.kmac_entropy_mode_error.2199603095 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 73261261 ps |
CPU time | 1.23 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:05:33 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-d2e6e029-11f1-46c2-a739-15179a53f473 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2199603095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2199603095 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2906170915 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 207753499 ps |
CPU time | 1.5 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 216172 kb |
Host | smart-34815a3c-b97c-4483-b443-03da6235e069 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906170915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.2906170915 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/11.kmac_lc_escalation.2411148730 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1010614469 ps |
CPU time | 14.7 seconds |
Started | Jul 13 05:09:50 PM PDT 24 |
Finished | Jul 13 05:10:05 PM PDT 24 |
Peak memory | 235688 kb |
Host | smart-ee96d2e7-3621-4829-a46b-d5c3116e5beb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411148730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2411148730 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/11.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/23.kmac_stress_all.1091765689 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 15969701380 ps |
CPU time | 1149.97 seconds |
Started | Jul 13 05:14:40 PM PDT 24 |
Finished | Jul 13 05:33:51 PM PDT 24 |
Peak memory | 339396 kb |
Host | smart-6016aad2-41c5-463d-8437-eef54d140e32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1091765689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1091765689 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_stress_all/latest |
Test location | /workspace/coverage/default/0.kmac_edn_timeout_error.1842223295 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 22932736 ps |
CPU time | 1.11 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:05:21 PM PDT 24 |
Peak memory | 218272 kb |
Host | smart-1d79f5a3-9af0-4ab9-a644-bc3f6c380ba6 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1842223295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1842223295 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/16.kmac_lc_escalation.375336743 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 61717004 ps |
CPU time | 1.21 seconds |
Started | Jul 13 05:12:00 PM PDT 24 |
Finished | Jul 13 05:12:02 PM PDT 24 |
Peak memory | 226544 kb |
Host | smart-efcfca16-cc29-4d52-8f49-ca82841c40f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375336743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.375336743 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/16.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_shake_128.2387427880 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2888494753404 ps |
CPU time | 6673.04 seconds |
Started | Jul 13 05:09:05 PM PDT 24 |
Finished | Jul 13 07:00:20 PM PDT 24 |
Peak memory | 660436 kb |
Host | smart-9b4a89b1-6b59-4bd4-88f7-987f07c5a06a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2387427880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2387427880 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2000471456 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 73559696 ps |
CPU time | 1.53 seconds |
Started | Jul 13 04:59:37 PM PDT 24 |
Finished | Jul 13 04:59:39 PM PDT 24 |
Peak memory | 215940 kb |
Host | smart-e5df07cc-00bb-4f58-a430-64346fa3f763 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000471456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2000471456 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.451470133 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 98802663 ps |
CPU time | 2.7 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 219848 kb |
Host | smart-8eca3d4a-67b7-4788-8683-014f5dff50f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451470133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac _shadow_reg_errors_with_csr_rw.451470133 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/default/1.kmac_alert_test.3077508342 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 37646386 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:05:32 PM PDT 24 |
Peak memory | 218276 kb |
Host | smart-3fc2a946-3203-4de9-80b7-01ec2f2787fe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077508342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3077508342 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_alert_test/latest |
Test location | /workspace/coverage/default/20.kmac_lc_escalation.2432379226 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 53884179 ps |
CPU time | 1.26 seconds |
Started | Jul 13 05:13:41 PM PDT 24 |
Finished | Jul 13 05:13:43 PM PDT 24 |
Peak memory | 226808 kb |
Host | smart-3ab1f366-0b29-4a27-8583-3f20cd8c1962 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432379226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2432379226 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/20.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/31.kmac_lc_escalation.7474289 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 35037150 ps |
CPU time | 1.52 seconds |
Started | Jul 13 05:17:49 PM PDT 24 |
Finished | Jul 13 05:17:51 PM PDT 24 |
Peak memory | 226516 kb |
Host | smart-023a6429-c852-40f1-9174-0b52ebfa8945 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7474289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.7474289 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_lc_escalation/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3354609547 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 467424120 ps |
CPU time | 4.91 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:53 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-d8f6335e-aaad-4346-bd19-8af3b41972b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354609547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.33546 09547 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1033181516 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 146495861 ps |
CPU time | 1.13 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:15 PM PDT 24 |
Peak memory | 216148 kb |
Host | smart-57f4553d-a835-43a3-b445-3771ea0e9a60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033181516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1033181516 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/30.kmac_entropy_refresh.2760363313 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 13174131626 ps |
CPU time | 228.74 seconds |
Started | Jul 13 05:17:28 PM PDT 24 |
Finished | Jul 13 05:21:17 PM PDT 24 |
Peak memory | 245776 kb |
Host | smart-c67cccab-923b-4745-919b-1dff8a9c26f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760363313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2760363313 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/30.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/4.kmac_key_error.1273378925 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 43327673 ps |
CPU time | 1.1 seconds |
Started | Jul 13 05:06:24 PM PDT 24 |
Finished | Jul 13 05:06:25 PM PDT 24 |
Peak memory | 222012 kb |
Host | smart-0026a7fb-0a4e-4555-aead-738bde7730db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273378925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1273378925 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_key_error/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_intr_test.3484235025 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 12311570 ps |
CPU time | 0.76 seconds |
Started | Jul 13 04:59:39 PM PDT 24 |
Finished | Jul 13 04:59:40 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-334814cf-cf20-4d56-aace-e98b2297792c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484235025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3484235025 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_intr_test/latest |
Test location | /workspace/coverage/default/0.kmac_smoke.278841218 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2476734001 ps |
CPU time | 40.9 seconds |
Started | Jul 13 05:05:16 PM PDT 24 |
Finished | Jul 13 05:05:57 PM PDT 24 |
Peak memory | 218820 kb |
Host | smart-c4f94dac-02f4-4159-ba7d-e9ebd7173419 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278841218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.278841218 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_smoke/latest |
Test location | /workspace/coverage/default/11.kmac_error.3320458214 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 15030764173 ps |
CPU time | 274.43 seconds |
Started | Jul 13 05:09:41 PM PDT 24 |
Finished | Jul 13 05:14:16 PM PDT 24 |
Peak memory | 259388 kb |
Host | smart-58415358-34f6-4783-957c-bfc68c44fb71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320458214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3320458214 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_error/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_intr_test.4169171597 |
Short name | T1119 |
Test name | |
Test status | |
Simulation time | 108948293 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 215728 kb |
Host | smart-11c46329-fc04-465d-bc78-b285aa6818ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169171597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4169171597 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4162600859 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 186443945 ps |
CPU time | 4.06 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:12 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-bcc09128-ae43-498e-8440-29fdbb3b49b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162600859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4162 600859 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/25.kmac_entropy_refresh.1026116548 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 17850783378 ps |
CPU time | 387.13 seconds |
Started | Jul 13 05:15:22 PM PDT 24 |
Finished | Jul 13 05:21:50 PM PDT 24 |
Peak memory | 250900 kb |
Host | smart-6df6e3a0-ba01-47ff-86f3-5ab3272053cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026116548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1026116548 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/25.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/0.kmac_sideload.2958208066 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 104905475771 ps |
CPU time | 278.93 seconds |
Started | Jul 13 05:05:11 PM PDT 24 |
Finished | Jul 13 05:09:51 PM PDT 24 |
Peak memory | 245280 kb |
Host | smart-a1195978-4361-44a8-8028-3cfc8584cf8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958208066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2958208066 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_sideload/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1695634720 |
Short name | T1147 |
Test name | |
Test status | |
Simulation time | 396377662 ps |
CPU time | 9.41 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:33 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-add6a717-af21-45cd-b09f-adbde8b05b58 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695634720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1695634 720 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2277916531 |
Short name | T1216 |
Test name | |
Test status | |
Simulation time | 164666653 ps |
CPU time | 8.56 seconds |
Started | Jul 13 04:59:24 PM PDT 24 |
Finished | Jul 13 04:59:33 PM PDT 24 |
Peak memory | 215996 kb |
Host | smart-beb2ccd9-4f0c-4170-87ff-9a44dc5c1959 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277916531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2277916 531 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2690742973 |
Short name | T1162 |
Test name | |
Test status | |
Simulation time | 60937588 ps |
CPU time | 0.96 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:24 PM PDT 24 |
Peak memory | 215684 kb |
Host | smart-6823f082-589e-43b5-84c1-9e8b9b930c00 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690742973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2690742 973 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4080718010 |
Short name | T1146 |
Test name | |
Test status | |
Simulation time | 44031408 ps |
CPU time | 1.68 seconds |
Started | Jul 13 04:59:24 PM PDT 24 |
Finished | Jul 13 04:59:26 PM PDT 24 |
Peak memory | 220388 kb |
Host | smart-17900131-3e52-42cf-bd26-f7a43e90f214 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080718010 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4080718010 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_rw.880162022 |
Short name | T1128 |
Test name | |
Test status | |
Simulation time | 26476782 ps |
CPU time | 0.94 seconds |
Started | Jul 13 04:59:22 PM PDT 24 |
Finished | Jul 13 04:59:23 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-c206228c-6367-46eb-a3ec-a51dd2630e14 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880162022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.880162022 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_intr_test.3902975703 |
Short name | T1124 |
Test name | |
Test status | |
Simulation time | 80779509 ps |
CPU time | 0.81 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:24 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-903d29f8-3e63-48be-ab23-a30b08f8b66e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902975703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3902975703 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4188822496 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 31431674 ps |
CPU time | 1.27 seconds |
Started | Jul 13 04:59:22 PM PDT 24 |
Finished | Jul 13 04:59:23 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-9acc0563-1130-4713-8cf3-764328367da1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188822496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.4188822496 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_mem_walk.4048154131 |
Short name | T1136 |
Test name | |
Test status | |
Simulation time | 12737161 ps |
CPU time | 0.77 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:24 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-49fca3d3-3d10-4237-8f74-ce7c4a2859d9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048154131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4048154131 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3591146938 |
Short name | T1137 |
Test name | |
Test status | |
Simulation time | 86942117 ps |
CPU time | 2.2 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:25 PM PDT 24 |
Peak memory | 215824 kb |
Host | smart-ce7326a7-c76c-418f-a9b9-890e9a74c06b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591146938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3591146938 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.586580130 |
Short name | T1084 |
Test name | |
Test status | |
Simulation time | 35691009 ps |
CPU time | 0.96 seconds |
Started | Jul 13 04:59:14 PM PDT 24 |
Finished | Jul 13 04:59:16 PM PDT 24 |
Peak memory | 216004 kb |
Host | smart-ed8cbc22-d280-45c0-8002-0aa56fb5242d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586580130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e rrors.586580130 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.906769262 |
Short name | T1172 |
Test name | |
Test status | |
Simulation time | 121073539 ps |
CPU time | 1.96 seconds |
Started | Jul 13 04:59:15 PM PDT 24 |
Finished | Jul 13 04:59:18 PM PDT 24 |
Peak memory | 216196 kb |
Host | smart-6515e183-db90-4188-9a93-7016f8b4288f |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906769262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.906769262 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_tl_errors.900121105 |
Short name | T1178 |
Test name | |
Test status | |
Simulation time | 203055499 ps |
CPU time | 2.07 seconds |
Started | Jul 13 04:59:23 PM PDT 24 |
Finished | Jul 13 04:59:26 PM PDT 24 |
Peak memory | 215888 kb |
Host | smart-3f91f587-cb91-466c-84e5-a213a17c0bf5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900121105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.900121105 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1274555899 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 265067645 ps |
CPU time | 2.92 seconds |
Started | Jul 13 04:59:22 PM PDT 24 |
Finished | Jul 13 04:59:25 PM PDT 24 |
Peak memory | 215820 kb |
Host | smart-bd8cf194-daeb-4754-8b93-67ea73c3e078 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274555899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.12745 55899 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.871211256 |
Short name | T1166 |
Test name | |
Test status | |
Simulation time | 1491041018 ps |
CPU time | 5.38 seconds |
Started | Jul 13 04:59:43 PM PDT 24 |
Finished | Jul 13 04:59:49 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-7aeed8d4-ad93-4069-b1b9-b188e540e257 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871211256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.87121125 6 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3906880817 |
Short name | T1134 |
Test name | |
Test status | |
Simulation time | 3917762598 ps |
CPU time | 20.36 seconds |
Started | Jul 13 04:59:43 PM PDT 24 |
Finished | Jul 13 05:00:03 PM PDT 24 |
Peak memory | 215992 kb |
Host | smart-18805a5a-4114-4176-a449-11310bdb12ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906880817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3906880 817 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.487994613 |
Short name | T1187 |
Test name | |
Test status | |
Simulation time | 56112655 ps |
CPU time | 1.13 seconds |
Started | Jul 13 04:59:37 PM PDT 24 |
Finished | Jul 13 04:59:39 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-8afd6009-0673-4153-8802-1faf550b51ce |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487994613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.48799461 3 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1158257171 |
Short name | T1205 |
Test name | |
Test status | |
Simulation time | 36319683 ps |
CPU time | 2.21 seconds |
Started | Jul 13 04:59:43 PM PDT 24 |
Finished | Jul 13 04:59:46 PM PDT 24 |
Peak memory | 221148 kb |
Host | smart-4df51c1c-fbf6-4d6d-a958-a15b041ef72c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158257171 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1158257171 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1530170323 |
Short name | T1114 |
Test name | |
Test status | |
Simulation time | 24949151 ps |
CPU time | 0.95 seconds |
Started | Jul 13 04:59:38 PM PDT 24 |
Finished | Jul 13 04:59:39 PM PDT 24 |
Peak memory | 215696 kb |
Host | smart-a25901cf-d142-4ad6-a814-8abb8f087891 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530170323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1530170323 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2619166050 |
Short name | T1090 |
Test name | |
Test status | |
Simulation time | 34937944 ps |
CPU time | 0.75 seconds |
Started | Jul 13 04:59:29 PM PDT 24 |
Finished | Jul 13 04:59:31 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-ec764783-c24a-43ee-9981-c3b927627dcb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619166050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2619166050 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.909886244 |
Short name | T1115 |
Test name | |
Test status | |
Simulation time | 266194284 ps |
CPU time | 1.66 seconds |
Started | Jul 13 04:59:44 PM PDT 24 |
Finished | Jul 13 04:59:46 PM PDT 24 |
Peak memory | 215816 kb |
Host | smart-d9cd6e29-7a21-42f5-986c-be0d076ac566 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909886244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_ outstanding.909886244 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.262368407 |
Short name | T1183 |
Test name | |
Test status | |
Simulation time | 80866020 ps |
CPU time | 0.99 seconds |
Started | Jul 13 04:59:30 PM PDT 24 |
Finished | Jul 13 04:59:31 PM PDT 24 |
Peak memory | 216060 kb |
Host | smart-b41adb5a-a5e7-4e00-a166-ef1b75c59989 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262368407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e rrors.262368407 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.545518601 |
Short name | T1190 |
Test name | |
Test status | |
Simulation time | 157334085 ps |
CPU time | 2.08 seconds |
Started | Jul 13 04:59:29 PM PDT 24 |
Finished | Jul 13 04:59:31 PM PDT 24 |
Peak memory | 218056 kb |
Host | smart-2c07f2bf-cdc3-44d9-a294-e06dfbd19a84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545518601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.545518601 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.kmac_tl_errors.531402778 |
Short name | T1200 |
Test name | |
Test status | |
Simulation time | 271855932 ps |
CPU time | 1.28 seconds |
Started | Jul 13 04:59:38 PM PDT 24 |
Finished | Jul 13 04:59:39 PM PDT 24 |
Peak memory | 215896 kb |
Host | smart-eb8e863f-4d9d-4a78-abf5-0727c10afcbb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531402778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.531402778 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.488925628 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 41473830 ps |
CPU time | 1.65 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 218308 kb |
Host | smart-47949e1c-9ad6-4871-a99d-951528f9765a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488925628 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.488925628 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_csr_rw.125957537 |
Short name | T1110 |
Test name | |
Test status | |
Simulation time | 69601964 ps |
CPU time | 1.18 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-345f01f4-4a31-41e3-8613-ae01a838c01d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125957537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.125957537 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_intr_test.237800952 |
Short name | T1144 |
Test name | |
Test status | |
Simulation time | 13936709 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:00:50 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 216032 kb |
Host | smart-f914393a-4df7-471d-922c-9c512641519d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237800952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.237800952 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1122803439 |
Short name | T1165 |
Test name | |
Test status | |
Simulation time | 82748905 ps |
CPU time | 1.65 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-a00f6226-3285-4e79-b0e5-aff0306b3a88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122803439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.1122803439 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1064281824 |
Short name | T1201 |
Test name | |
Test status | |
Simulation time | 42109771 ps |
CPU time | 2.11 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 215884 kb |
Host | smart-f9057d4f-bac0-4be5-ba58-372ca9bec9fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064281824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1064281824 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.4174110271 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 126746702 ps |
CPU time | 2.89 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-fca76417-87b5-45f8-a4aa-569a81795409 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174110271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.4174 110271 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2500489219 |
Short name | T1196 |
Test name | |
Test status | |
Simulation time | 577632927 ps |
CPU time | 2.32 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 220912 kb |
Host | smart-81b8cd47-9680-4d11-9106-04c66aaa2294 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500489219 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2500489219 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_csr_rw.506468324 |
Short name | T1129 |
Test name | |
Test status | |
Simulation time | 66171152 ps |
CPU time | 0.99 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 215700 kb |
Host | smart-041d8b44-c012-4e26-bd95-4c18cd1387d4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506468324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.506468324 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_intr_test.1230293382 |
Short name | T1113 |
Test name | |
Test status | |
Simulation time | 14687482 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 215732 kb |
Host | smart-0fcc3cb1-3490-4476-8aa5-db99b3f4135e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230293382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1230293382 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3968565161 |
Short name | T1185 |
Test name | |
Test status | |
Simulation time | 108109063 ps |
CPU time | 2.57 seconds |
Started | Jul 13 05:00:49 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-0e2877b2-0051-4e2c-8ab9-7806178c32d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968565161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.3968565161 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2361693259 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 71740657 ps |
CPU time | 1.25 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:49 PM PDT 24 |
Peak memory | 216396 kb |
Host | smart-0baa3420-5a31-409a-85f7-969393ba4a23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361693259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.2361693259 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2233600483 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 222661535 ps |
CPU time | 1.8 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 215872 kb |
Host | smart-5329b364-fd2e-4dd2-ba25-2b7d52439adf |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233600483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.2233600483 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2512842714 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 149283309 ps |
CPU time | 1.49 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:49 PM PDT 24 |
Peak memory | 215928 kb |
Host | smart-65c518e9-6665-4db1-b705-5b479d2d0686 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512842714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2512842714 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.49760462 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 374800565 ps |
CPU time | 4.13 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:53 PM PDT 24 |
Peak memory | 215748 kb |
Host | smart-1044334e-c6c2-489e-ad60-6642f69cc49f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49760462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.497604 62 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1075439640 |
Short name | T1142 |
Test name | |
Test status | |
Simulation time | 85927870 ps |
CPU time | 1.78 seconds |
Started | Jul 13 05:00:50 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 219960 kb |
Host | smart-492943d5-d934-4652-8c25-fc4f5ebbc4ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075439640 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1075439640 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1761277283 |
Short name | T1153 |
Test name | |
Test status | |
Simulation time | 23456613 ps |
CPU time | 1.01 seconds |
Started | Jul 13 05:00:51 PM PDT 24 |
Finished | Jul 13 05:00:53 PM PDT 24 |
Peak memory | 215724 kb |
Host | smart-0c9e0a17-f166-464b-a657-e19769338591 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761277283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1761277283 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_intr_test.2286824911 |
Short name | T1221 |
Test name | |
Test status | |
Simulation time | 50407399 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:00:51 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 215716 kb |
Host | smart-791510c3-c7b6-4bd5-9179-840023db7389 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286824911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2286824911 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1549463666 |
Short name | T1080 |
Test name | |
Test status | |
Simulation time | 471490919 ps |
CPU time | 2.46 seconds |
Started | Jul 13 05:00:51 PM PDT 24 |
Finished | Jul 13 05:00:54 PM PDT 24 |
Peak memory | 215788 kb |
Host | smart-d287b0a6-6439-4f51-896a-54637df502f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549463666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.1549463666 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.468358422 |
Short name | T1161 |
Test name | |
Test status | |
Simulation time | 35310744 ps |
CPU time | 1.26 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:53 PM PDT 24 |
Peak memory | 216096 kb |
Host | smart-a3a9bbe0-a8cd-469d-8adc-ada0f43d6680 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468358422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_ errors.468358422 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1245238332 |
Short name | T1211 |
Test name | |
Test status | |
Simulation time | 103620165 ps |
CPU time | 1.68 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:55 PM PDT 24 |
Peak memory | 218292 kb |
Host | smart-cafa5e5b-e676-40ee-a2d2-8568174176ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245238332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.1245238332 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3734986257 |
Short name | T1223 |
Test name | |
Test status | |
Simulation time | 56066954 ps |
CPU time | 2.02 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:54 PM PDT 24 |
Peak memory | 215852 kb |
Host | smart-e75bc0b9-679b-4ed8-9ba4-3b8147d186d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734986257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3734986257 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3221384325 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 145465314 ps |
CPU time | 4.27 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:57 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-bbb17e42-f3ff-4505-bb2b-9dc46dd85a75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221384325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3221 384325 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2378125368 |
Short name | T1186 |
Test name | |
Test status | |
Simulation time | 68917196 ps |
CPU time | 2.25 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:02 PM PDT 24 |
Peak memory | 222032 kb |
Host | smart-b49ba51d-532f-4d57-874e-e4fd19886a0a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378125368 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2378125368 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_csr_rw.414548333 |
Short name | T1225 |
Test name | |
Test status | |
Simulation time | 39520948 ps |
CPU time | 0.96 seconds |
Started | Jul 13 05:00:58 PM PDT 24 |
Finished | Jul 13 05:00:59 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-05724b50-f3d7-492c-acee-fdfdeb7b575f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414548333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.414548333 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_intr_test.369030929 |
Short name | T1182 |
Test name | |
Test status | |
Simulation time | 33319509 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:01:01 PM PDT 24 |
Finished | Jul 13 05:01:02 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-ef6bd9e7-3977-4c25-a286-ebfb23d1c204 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369030929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.369030929 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.160621608 |
Short name | T1116 |
Test name | |
Test status | |
Simulation time | 175439507 ps |
CPU time | 1.61 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:01 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-4e8d7f06-a492-467d-946f-2cccef496af6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160621608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr _outstanding.160621608 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2310066718 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 84560966 ps |
CPU time | 1.38 seconds |
Started | Jul 13 05:00:50 PM PDT 24 |
Finished | Jul 13 05:00:52 PM PDT 24 |
Peak memory | 217228 kb |
Host | smart-b39a30ae-4e43-4486-b8cb-7acbca6dea52 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310066718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.2310066718 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2754729441 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 56426574 ps |
CPU time | 2.56 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:55 PM PDT 24 |
Peak memory | 218328 kb |
Host | smart-291cef76-1192-40d0-9ebb-f1679b838473 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754729441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.2754729441 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1450712046 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 183271096 ps |
CPU time | 3.25 seconds |
Started | Jul 13 05:00:52 PM PDT 24 |
Finished | Jul 13 05:00:56 PM PDT 24 |
Peak memory | 215984 kb |
Host | smart-7eda2781-0e33-435b-8f77-5f115b6aa58f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450712046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1450712046 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.838749475 |
Short name | T1104 |
Test name | |
Test status | |
Simulation time | 226044146 ps |
CPU time | 2.44 seconds |
Started | Jul 13 05:00:50 PM PDT 24 |
Finished | Jul 13 05:00:54 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-6da7e5e9-a00e-4708-ae87-f8ed0918c16b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838749475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.83874 9475 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4126385457 |
Short name | T1193 |
Test name | |
Test status | |
Simulation time | 135131753 ps |
CPU time | 1.63 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 216844 kb |
Host | smart-7ed539d1-e06b-4c4c-adc8-4c47638af4ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126385457 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.4126385457 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_csr_rw.312084676 |
Short name | T1098 |
Test name | |
Test status | |
Simulation time | 29645259 ps |
CPU time | 0.99 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:00 PM PDT 24 |
Peak memory | 215736 kb |
Host | smart-22eb2620-f548-4b73-b72b-63a735d2a89b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312084676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.312084676 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_intr_test.2762563942 |
Short name | T1112 |
Test name | |
Test status | |
Simulation time | 15155201 ps |
CPU time | 0.86 seconds |
Started | Jul 13 05:01:01 PM PDT 24 |
Finished | Jul 13 05:01:02 PM PDT 24 |
Peak memory | 215776 kb |
Host | smart-a475f862-4bf2-4a7e-9e50-7f76849fbc9d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762563942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2762563942 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2969619452 |
Short name | T1199 |
Test name | |
Test status | |
Simulation time | 808309747 ps |
CPU time | 1.93 seconds |
Started | Jul 13 05:01:09 PM PDT 24 |
Finished | Jul 13 05:01:11 PM PDT 24 |
Peak memory | 215992 kb |
Host | smart-a49d1316-b549-4f02-affe-5f4d0380c87f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969619452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.2969619452 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.599899068 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 51244354 ps |
CPU time | 1.27 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:00 PM PDT 24 |
Peak memory | 216128 kb |
Host | smart-432caca7-4855-4c49-82b0-c5ff94d81a42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599899068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_ errors.599899068 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2652056578 |
Short name | T1132 |
Test name | |
Test status | |
Simulation time | 237521100 ps |
CPU time | 1.84 seconds |
Started | Jul 13 05:01:01 PM PDT 24 |
Finished | Jul 13 05:01:03 PM PDT 24 |
Peak memory | 219408 kb |
Host | smart-b46fb9b7-3c7a-4f9c-bd1b-3ea88d3ca9cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652056578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.2652056578 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1289351720 |
Short name | T1164 |
Test name | |
Test status | |
Simulation time | 38641948 ps |
CPU time | 2.86 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:03 PM PDT 24 |
Peak memory | 215928 kb |
Host | smart-d18e5ee0-c4b4-43ff-bf2b-0625fbc01739 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289351720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1289351720 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1564860070 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 96393497 ps |
CPU time | 2.58 seconds |
Started | Jul 13 05:00:59 PM PDT 24 |
Finished | Jul 13 05:01:02 PM PDT 24 |
Peak memory | 215856 kb |
Host | smart-a40b4b21-c07c-4f8a-afc0-46c25cbda2ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564860070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1564 860070 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2417842344 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 80333456 ps |
CPU time | 1.49 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 216888 kb |
Host | smart-1afc117e-5c97-43cb-a1d7-107cc012110d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417842344 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2417842344 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_csr_rw.877452297 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 99469204 ps |
CPU time | 1.13 seconds |
Started | Jul 13 05:01:08 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 215828 kb |
Host | smart-1623b5b6-ffb5-4ddc-a540-fad673994377 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877452297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.877452297 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2435438786 |
Short name | T1204 |
Test name | |
Test status | |
Simulation time | 321091018 ps |
CPU time | 2.38 seconds |
Started | Jul 13 05:01:09 PM PDT 24 |
Finished | Jul 13 05:01:12 PM PDT 24 |
Peak memory | 216080 kb |
Host | smart-a95092fa-405d-4890-96d1-3ef4a36be375 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435438786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2435438786 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.4251390874 |
Short name | T1171 |
Test name | |
Test status | |
Simulation time | 96601243 ps |
CPU time | 1.22 seconds |
Started | Jul 13 05:01:09 PM PDT 24 |
Finished | Jul 13 05:01:11 PM PDT 24 |
Peak memory | 216140 kb |
Host | smart-3d82d017-170c-491a-9904-ddf095e5102a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251390874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.4251390874 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.987519537 |
Short name | T1227 |
Test name | |
Test status | |
Simulation time | 104454547 ps |
CPU time | 1.73 seconds |
Started | Jul 13 05:01:06 PM PDT 24 |
Finished | Jul 13 05:01:08 PM PDT 24 |
Peak memory | 218008 kb |
Host | smart-f8334e88-53d2-4ae6-862b-d1838d6d672a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987519537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac _shadow_reg_errors_with_csr_rw.987519537 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3256437649 |
Short name | T1151 |
Test name | |
Test status | |
Simulation time | 164688618 ps |
CPU time | 2.69 seconds |
Started | Jul 13 05:01:06 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 215848 kb |
Host | smart-9aa12f49-1cb1-4cbc-a858-66ebcfc4b492 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256437649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3256437649 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2350910040 |
Short name | T1168 |
Test name | |
Test status | |
Simulation time | 230121363 ps |
CPU time | 2.52 seconds |
Started | Jul 13 05:01:09 PM PDT 24 |
Finished | Jul 13 05:01:12 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-e451938e-97d0-4c61-897f-2e304b13c77d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350910040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2350 910040 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3541487166 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 82743131 ps |
CPU time | 1.74 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:16 PM PDT 24 |
Peak memory | 217500 kb |
Host | smart-1a33ed07-7ba2-433f-9df7-f1a06e0060ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541487166 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3541487166 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_csr_rw.170917621 |
Short name | T1197 |
Test name | |
Test status | |
Simulation time | 28086279 ps |
CPU time | 1.03 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215680 kb |
Host | smart-b8547cdb-97f9-4570-8a65-819e9a0fbb6f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170917621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.170917621 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_intr_test.984069076 |
Short name | T1099 |
Test name | |
Test status | |
Simulation time | 15200238 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:15 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-746ea626-a09c-46f3-92bf-f2df76179962 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984069076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.984069076 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3062570314 |
Short name | T1081 |
Test name | |
Test status | |
Simulation time | 28773108 ps |
CPU time | 1.71 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215820 kb |
Host | smart-3a1e0633-2bc3-45e5-b56b-0d65081b5437 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062570314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.3062570314 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.413526445 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 18966222 ps |
CPU time | 0.99 seconds |
Started | Jul 13 05:01:06 PM PDT 24 |
Finished | Jul 13 05:01:07 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-702c12fd-8a03-4f41-a83c-2f7aa2e05128 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413526445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_ errors.413526445 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3268128236 |
Short name | T1138 |
Test name | |
Test status | |
Simulation time | 269935273 ps |
CPU time | 1.72 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 215796 kb |
Host | smart-34d5bb9f-2596-4c11-b816-81cd4c0793f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268128236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.3268128236 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1206086533 |
Short name | T1224 |
Test name | |
Test status | |
Simulation time | 220851538 ps |
CPU time | 1.77 seconds |
Started | Jul 13 05:01:07 PM PDT 24 |
Finished | Jul 13 05:01:09 PM PDT 24 |
Peak memory | 215876 kb |
Host | smart-c9591d20-705d-4562-88d2-de25c93bc8a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206086533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1206086533 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4068006486 |
Short name | T1232 |
Test name | |
Test status | |
Simulation time | 29877980 ps |
CPU time | 1.8 seconds |
Started | Jul 13 05:01:17 PM PDT 24 |
Finished | Jul 13 05:01:20 PM PDT 24 |
Peak memory | 220840 kb |
Host | smart-53c3fde2-9ab8-40eb-b38d-56121a056505 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068006486 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.4068006486 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1802606532 |
Short name | T1108 |
Test name | |
Test status | |
Simulation time | 42423766 ps |
CPU time | 1.07 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-ecfbfddf-5ea9-48a9-9c84-f848f8acd385 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802606532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1802606532 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_intr_test.1355218760 |
Short name | T1139 |
Test name | |
Test status | |
Simulation time | 18425788 ps |
CPU time | 0.9 seconds |
Started | Jul 13 05:01:16 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215724 kb |
Host | smart-6a478b8a-1c2e-41ba-a3f7-f685889f7208 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355218760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1355218760 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.325938612 |
Short name | T1088 |
Test name | |
Test status | |
Simulation time | 27508516 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:15 PM PDT 24 |
Peak memory | 215796 kb |
Host | smart-08f0a3a1-f218-4632-8c78-31d58c9f6a0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325938612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr _outstanding.325938612 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1126336367 |
Short name | T1158 |
Test name | |
Test status | |
Simulation time | 45551415 ps |
CPU time | 1.37 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 216136 kb |
Host | smart-2ba47950-91ab-47c5-8947-e962f308bf63 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126336367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.1126336367 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3288904979 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 75901921 ps |
CPU time | 2.02 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 218508 kb |
Host | smart-617c6c72-2f82-45f6-a110-cf150e6ec972 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288904979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.3288904979 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4087976308 |
Short name | T1176 |
Test name | |
Test status | |
Simulation time | 115382686 ps |
CPU time | 1.94 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:18 PM PDT 24 |
Peak memory | 215924 kb |
Host | smart-a2f4de35-3c3e-4789-a222-e288c88a420e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087976308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.4087976308 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.8513530 |
Short name | T1135 |
Test name | |
Test status | |
Simulation time | 104850411 ps |
CPU time | 2.87 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:19 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-b8b9278d-150e-45f1-85c1-29e5c18db5da |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8513530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.8513530 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4125649925 |
Short name | T1228 |
Test name | |
Test status | |
Simulation time | 75341186 ps |
CPU time | 1.66 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215944 kb |
Host | smart-fb5b0ab1-369d-4ebb-9f8a-de2da1513f94 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125649925 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.4125649925 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1344832185 |
Short name | T1220 |
Test name | |
Test status | |
Simulation time | 127129473 ps |
CPU time | 1.21 seconds |
Started | Jul 13 05:01:17 PM PDT 24 |
Finished | Jul 13 05:01:19 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-1547ff9e-b163-45d2-acc5-5416c0b14e99 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344832185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1344832185 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_intr_test.2422878852 |
Short name | T1118 |
Test name | |
Test status | |
Simulation time | 17806166 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-3a03f804-a7e9-48f1-87ab-155b5e8e6212 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422878852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2422878852 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1518211263 |
Short name | T1167 |
Test name | |
Test status | |
Simulation time | 150278045 ps |
CPU time | 2.33 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:18 PM PDT 24 |
Peak memory | 215816 kb |
Host | smart-a635f7a9-043a-489e-8d71-064e8e79a353 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518211263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.1518211263 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3532174819 |
Short name | T1141 |
Test name | |
Test status | |
Simulation time | 105445204 ps |
CPU time | 1.58 seconds |
Started | Jul 13 05:01:14 PM PDT 24 |
Finished | Jul 13 05:01:16 PM PDT 24 |
Peak memory | 216124 kb |
Host | smart-714ce42a-033e-42e1-b28f-5ccb3bcc7e3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532174819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.3532174819 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3588685719 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 144720345 ps |
CPU time | 2.58 seconds |
Started | Jul 13 05:01:16 PM PDT 24 |
Finished | Jul 13 05:01:19 PM PDT 24 |
Peak memory | 215924 kb |
Host | smart-77932433-6c71-42ad-8cf5-b2a6d393cb1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588685719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3588685719 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3254721686 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 192225370 ps |
CPU time | 4.13 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:19 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-f3d0ebc6-c0d4-4470-9f3d-341cd29a1d20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254721686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3254 721686 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1198254301 |
Short name | T1229 |
Test name | |
Test status | |
Simulation time | 162371205 ps |
CPU time | 1.59 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 217720 kb |
Host | smart-24f511cf-7bcf-4546-84fc-e59eaa866297 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198254301 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1198254301 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_csr_rw.989376507 |
Short name | T1140 |
Test name | |
Test status | |
Simulation time | 34685886 ps |
CPU time | 1.15 seconds |
Started | Jul 13 05:01:22 PM PDT 24 |
Finished | Jul 13 05:01:24 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-d689d245-5281-4012-baf4-e8df41238b24 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989376507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.989376507 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_intr_test.2242069533 |
Short name | T1179 |
Test name | |
Test status | |
Simulation time | 16066755 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:01:23 PM PDT 24 |
Finished | Jul 13 05:01:24 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-2633a3c6-fc28-4c8b-9b81-128b50164e3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242069533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2242069533 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1800474692 |
Short name | T1218 |
Test name | |
Test status | |
Simulation time | 116199139 ps |
CPU time | 1.7 seconds |
Started | Jul 13 05:01:28 PM PDT 24 |
Finished | Jul 13 05:01:30 PM PDT 24 |
Peak memory | 215800 kb |
Host | smart-0dbeb33d-5c21-4126-9f70-dba3299d5993 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800474692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.1800474692 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3590112965 |
Short name | T1219 |
Test name | |
Test status | |
Simulation time | 87694340 ps |
CPU time | 1.48 seconds |
Started | Jul 13 05:01:15 PM PDT 24 |
Finished | Jul 13 05:01:17 PM PDT 24 |
Peak memory | 217124 kb |
Host | smart-8288c5bb-b532-4cc8-81a4-ab317129bd74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590112965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.3590112965 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1319138900 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 44705554 ps |
CPU time | 2.11 seconds |
Started | Jul 13 05:01:21 PM PDT 24 |
Finished | Jul 13 05:01:24 PM PDT 24 |
Peak memory | 217764 kb |
Host | smart-cb7cf337-b240-4618-a3d4-6a1dc284b2a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319138900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.1319138900 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2284673709 |
Short name | T1180 |
Test name | |
Test status | |
Simulation time | 28443898 ps |
CPU time | 1.56 seconds |
Started | Jul 13 05:01:23 PM PDT 24 |
Finished | Jul 13 05:01:25 PM PDT 24 |
Peak memory | 215908 kb |
Host | smart-7811ed48-4192-4564-93c0-1a71fb48c885 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284673709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2284673709 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3179268374 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 885595682 ps |
CPU time | 4.99 seconds |
Started | Jul 13 05:01:23 PM PDT 24 |
Finished | Jul 13 05:01:28 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-b6786d4a-d3ad-4bdb-a094-7386fe0d96a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179268374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3179 268374 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2114140247 |
Short name | T1087 |
Test name | |
Test status | |
Simulation time | 773152771 ps |
CPU time | 9.36 seconds |
Started | Jul 13 04:59:58 PM PDT 24 |
Finished | Jul 13 05:00:08 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-a74dab54-5b20-4aab-ba25-79a00392d74f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114140247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2114140 247 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1741566516 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 428658271 ps |
CPU time | 8.63 seconds |
Started | Jul 13 04:59:57 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-67627de7-cfda-4f57-ae9a-9ddc053d9e29 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741566516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1741566 516 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.810400983 |
Short name | T1192 |
Test name | |
Test status | |
Simulation time | 57727758 ps |
CPU time | 1.16 seconds |
Started | Jul 13 04:59:49 PM PDT 24 |
Finished | Jul 13 04:59:50 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-b874cfe9-8141-477e-a109-d6000f93b89f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810400983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.81040098 3 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3717472535 |
Short name | T1152 |
Test name | |
Test status | |
Simulation time | 36196831 ps |
CPU time | 1.54 seconds |
Started | Jul 13 04:59:57 PM PDT 24 |
Finished | Jul 13 04:59:59 PM PDT 24 |
Peak memory | 217448 kb |
Host | smart-bba1620c-4a05-4aef-a9d9-1cae597d7e66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717472535 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3717472535 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3927630427 |
Short name | T1233 |
Test name | |
Test status | |
Simulation time | 17536479 ps |
CPU time | 1.15 seconds |
Started | Jul 13 04:59:59 PM PDT 24 |
Finished | Jul 13 05:00:00 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-3a7c32f7-1630-444b-8a1e-acc3e0485846 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927630427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3927630427 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1706502026 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 21530101 ps |
CPU time | 1.52 seconds |
Started | Jul 13 04:59:44 PM PDT 24 |
Finished | Jul 13 04:59:46 PM PDT 24 |
Peak memory | 215824 kb |
Host | smart-694e16c3-6285-4a00-b20e-9be113efc08c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706502026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.1706502026 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4014284962 |
Short name | T1103 |
Test name | |
Test status | |
Simulation time | 16579721 ps |
CPU time | 0.75 seconds |
Started | Jul 13 04:59:43 PM PDT 24 |
Finished | Jul 13 04:59:44 PM PDT 24 |
Peak memory | 215788 kb |
Host | smart-c8261f8f-cbda-4b61-ba8f-8cb3000a338b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014284962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4014284962 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3872918333 |
Short name | T1184 |
Test name | |
Test status | |
Simulation time | 1255436464 ps |
CPU time | 2.61 seconds |
Started | Jul 13 04:59:58 PM PDT 24 |
Finished | Jul 13 05:00:01 PM PDT 24 |
Peak memory | 215800 kb |
Host | smart-db40d0af-e01f-4275-8e71-16027277c786 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872918333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.3872918333 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.350802755 |
Short name | T1085 |
Test name | |
Test status | |
Simulation time | 125106790 ps |
CPU time | 0.99 seconds |
Started | Jul 13 04:59:43 PM PDT 24 |
Finished | Jul 13 04:59:44 PM PDT 24 |
Peak memory | 216036 kb |
Host | smart-0b868ec1-041a-4236-a036-159a553f4759 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350802755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e rrors.350802755 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3841567027 |
Short name | T1148 |
Test name | |
Test status | |
Simulation time | 33264223 ps |
CPU time | 1.58 seconds |
Started | Jul 13 04:59:44 PM PDT 24 |
Finished | Jul 13 04:59:46 PM PDT 24 |
Peak memory | 216228 kb |
Host | smart-57fadbf8-00ab-4755-bd1f-04bdbc9b3b9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841567027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.3841567027 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2712246974 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 87205286 ps |
CPU time | 2.87 seconds |
Started | Jul 13 04:59:50 PM PDT 24 |
Finished | Jul 13 04:59:53 PM PDT 24 |
Peak memory | 215920 kb |
Host | smart-cdfa3cfe-c259-4b40-98ea-0e35614c0ebd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712246974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2712246974 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.224271468 |
Short name | T1210 |
Test name | |
Test status | |
Simulation time | 333125331 ps |
CPU time | 3.96 seconds |
Started | Jul 13 04:59:50 PM PDT 24 |
Finished | Jul 13 04:59:54 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-ee57714e-3e68-4e8e-a867-0cb800047693 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224271468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.224271 468 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.kmac_intr_test.3972112914 |
Short name | T1194 |
Test name | |
Test status | |
Simulation time | 14418492 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-1387c4c3-7f2a-47fe-aef6-1966981ab96c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972112914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3972112914 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.kmac_intr_test.3748423059 |
Short name | T1093 |
Test name | |
Test status | |
Simulation time | 69622053 ps |
CPU time | 0.78 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-4e252e61-e1da-4f8d-887f-7d28a33e0937 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748423059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3748423059 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.kmac_intr_test.2410502707 |
Short name | T1191 |
Test name | |
Test status | |
Simulation time | 42984830 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:32 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-eb9bcb50-a862-4be4-8447-e55a2469b9c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410502707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2410502707 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.kmac_intr_test.3064502559 |
Short name | T1126 |
Test name | |
Test status | |
Simulation time | 17987616 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:31 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-4f362ec7-a4a1-411d-9f1e-913ba948334a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064502559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3064502559 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.kmac_intr_test.2412713618 |
Short name | T1149 |
Test name | |
Test status | |
Simulation time | 23060549 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-fcf425bd-1c5b-4faf-871c-2ccc64cd9d13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412713618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2412713618 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.kmac_intr_test.2284000421 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 16500590 ps |
CPU time | 0.85 seconds |
Started | Jul 13 05:01:28 PM PDT 24 |
Finished | Jul 13 05:01:30 PM PDT 24 |
Peak memory | 215740 kb |
Host | smart-6c0a6fd9-612a-4bd2-96e7-f4e59aac21a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284000421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2284000421 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.kmac_intr_test.2144882871 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 86024684 ps |
CPU time | 0.77 seconds |
Started | Jul 13 05:01:33 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-78350859-b852-454c-a7bc-9555e7806c84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144882871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2144882871 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.kmac_intr_test.1350987547 |
Short name | T1212 |
Test name | |
Test status | |
Simulation time | 40749140 ps |
CPU time | 0.77 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-4c5dc682-f6c5-437e-bd21-c5ea5cbd3417 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350987547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1350987547 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.kmac_intr_test.1122327684 |
Short name | T1130 |
Test name | |
Test status | |
Simulation time | 39253174 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:01:31 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215740 kb |
Host | smart-49b20ae7-1a86-441e-8e5e-4c6692a7d82b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122327684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1122327684 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.kmac_intr_test.4217221933 |
Short name | T1222 |
Test name | |
Test status | |
Simulation time | 14749765 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:01:32 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215724 kb |
Host | smart-a188fb0d-892c-494a-a3f3-b18fb8303f78 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217221933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4217221933 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2079983390 |
Short name | T1215 |
Test name | |
Test status | |
Simulation time | 518564891 ps |
CPU time | 7.46 seconds |
Started | Jul 13 05:00:05 PM PDT 24 |
Finished | Jul 13 05:00:13 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-c7b06adb-0c86-49d2-9aaf-13693b98b8e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079983390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2079983 390 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1561584187 |
Short name | T1107 |
Test name | |
Test status | |
Simulation time | 2018083936 ps |
CPU time | 9.71 seconds |
Started | Jul 13 05:00:07 PM PDT 24 |
Finished | Jul 13 05:00:17 PM PDT 24 |
Peak memory | 215868 kb |
Host | smart-324cae08-ff45-46a0-93a7-a43bfad9b492 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561584187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1561584 187 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1102738859 |
Short name | T1208 |
Test name | |
Test status | |
Simulation time | 70968798 ps |
CPU time | 0.95 seconds |
Started | Jul 13 05:00:04 PM PDT 24 |
Finished | Jul 13 05:00:05 PM PDT 24 |
Peak memory | 215740 kb |
Host | smart-6939bc6d-6def-4ad7-bd52-f1e9b8a4c014 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102738859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1102738 859 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.411865228 |
Short name | T1102 |
Test name | |
Test status | |
Simulation time | 162803434 ps |
CPU time | 2.4 seconds |
Started | Jul 13 05:00:05 PM PDT 24 |
Finished | Jul 13 05:00:07 PM PDT 24 |
Peak memory | 221420 kb |
Host | smart-da3ccf17-dcdd-4680-8b90-3d1562273985 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411865228 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.411865228 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2146535842 |
Short name | T1106 |
Test name | |
Test status | |
Simulation time | 26750505 ps |
CPU time | 1.17 seconds |
Started | Jul 13 05:00:04 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-24a4cfeb-cd8c-449b-89bd-7e21d9634134 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146535842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2146535842 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_intr_test.332436920 |
Short name | T1214 |
Test name | |
Test status | |
Simulation time | 164735901 ps |
CPU time | 0.78 seconds |
Started | Jul 13 05:00:06 PM PDT 24 |
Finished | Jul 13 05:00:07 PM PDT 24 |
Peak memory | 215732 kb |
Host | smart-4a6909da-2748-4318-a8c5-931e5e70ab87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332436920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.332436920 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2793039354 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 54590239 ps |
CPU time | 1.52 seconds |
Started | Jul 13 05:00:00 PM PDT 24 |
Finished | Jul 13 05:00:02 PM PDT 24 |
Peak memory | 216080 kb |
Host | smart-bce3df3a-64f5-427d-b980-6c07cccb154d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793039354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.2793039354 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1196244939 |
Short name | T1145 |
Test name | |
Test status | |
Simulation time | 29142768 ps |
CPU time | 0.74 seconds |
Started | Jul 13 04:59:56 PM PDT 24 |
Finished | Jul 13 04:59:57 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-d2148820-1931-45cd-bf79-536b9b7880c9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196244939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1196244939 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3198944782 |
Short name | T1101 |
Test name | |
Test status | |
Simulation time | 113111735 ps |
CPU time | 1.64 seconds |
Started | Jul 13 05:00:04 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 215816 kb |
Host | smart-57134a4b-db82-4653-9bef-1af6ac057b70 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198944782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3198944782 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1963868049 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 182404109 ps |
CPU time | 1.24 seconds |
Started | Jul 13 04:59:58 PM PDT 24 |
Finished | Jul 13 04:59:59 PM PDT 24 |
Peak memory | 217192 kb |
Host | smart-1258f799-939b-49a4-bcfd-bd0abe891b8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963868049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.1963868049 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1423912660 |
Short name | T1181 |
Test name | |
Test status | |
Simulation time | 497063571 ps |
CPU time | 2.67 seconds |
Started | Jul 13 04:59:58 PM PDT 24 |
Finished | Jul 13 05:00:01 PM PDT 24 |
Peak memory | 219260 kb |
Host | smart-89bd2835-cbda-4a13-90fa-864653f49367 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423912660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.1423912660 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3440753693 |
Short name | T1173 |
Test name | |
Test status | |
Simulation time | 173427103 ps |
CPU time | 1.78 seconds |
Started | Jul 13 05:00:06 PM PDT 24 |
Finished | Jul 13 05:00:08 PM PDT 24 |
Peak memory | 215920 kb |
Host | smart-ffff98c5-bfba-4e93-adf1-5f4497a72e56 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440753693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3440753693 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1837121577 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 111640306 ps |
CPU time | 4.02 seconds |
Started | Jul 13 05:00:06 PM PDT 24 |
Finished | Jul 13 05:00:10 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-986f5218-10e4-4b99-8813-0ee64bd50271 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837121577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.18371 21577 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.kmac_intr_test.1568616807 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 29253498 ps |
CPU time | 0.76 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-91f49102-fb63-41af-986c-4261fb151666 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568616807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1568616807 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.kmac_intr_test.1646710626 |
Short name | T1089 |
Test name | |
Test status | |
Simulation time | 44062419 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:31 PM PDT 24 |
Peak memory | 215732 kb |
Host | smart-cf209a7a-00b2-49a9-90b3-ba56520edc45 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646710626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1646710626 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.kmac_intr_test.3919772440 |
Short name | T1157 |
Test name | |
Test status | |
Simulation time | 25960340 ps |
CPU time | 0.78 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:31 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-b715bae9-d6fe-4102-ac7f-fe31bb28ddd0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919772440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3919772440 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.kmac_intr_test.2441364212 |
Short name | T1094 |
Test name | |
Test status | |
Simulation time | 16981615 ps |
CPU time | 0.85 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-76234628-5a5b-47d5-833c-87ca497954ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441364212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2441364212 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.kmac_intr_test.3054291936 |
Short name | T1120 |
Test name | |
Test status | |
Simulation time | 82359988 ps |
CPU time | 0.85 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215724 kb |
Host | smart-0ee4f737-938a-4a31-987a-1c98e203eba1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054291936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3054291936 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.kmac_intr_test.2937621199 |
Short name | T1143 |
Test name | |
Test status | |
Simulation time | 102582744 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:01:33 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-5688d164-d2bd-4283-9a24-8053088d8754 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937621199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2937621199 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.kmac_intr_test.1652893855 |
Short name | T1100 |
Test name | |
Test status | |
Simulation time | 21736192 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:31 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 216032 kb |
Host | smart-05138922-50fc-4ea3-b503-24ffba94afa8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652893855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1652893855 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.kmac_intr_test.607241834 |
Short name | T1217 |
Test name | |
Test status | |
Simulation time | 46156440 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:01:31 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-9c7aaf74-f153-414e-bc6a-46fe279b4280 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607241834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.607241834 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.kmac_intr_test.288617576 |
Short name | T1117 |
Test name | |
Test status | |
Simulation time | 11960658 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-4bf5d327-4450-46fb-8372-19fe1e97df44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288617576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.288617576 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.kmac_intr_test.3751204119 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 11651392 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:31 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-7fc2054c-deb6-42f9-902d-73a7e1bc6118 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751204119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3751204119 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3048337778 |
Short name | T1109 |
Test name | |
Test status | |
Simulation time | 494627085 ps |
CPU time | 9.47 seconds |
Started | Jul 13 05:00:15 PM PDT 24 |
Finished | Jul 13 05:00:25 PM PDT 24 |
Peak memory | 215800 kb |
Host | smart-0312235f-ddd2-40ff-a25b-8931f9ecd9b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048337778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3048337 778 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2203969606 |
Short name | T1121 |
Test name | |
Test status | |
Simulation time | 292818939 ps |
CPU time | 16.24 seconds |
Started | Jul 13 05:00:12 PM PDT 24 |
Finished | Jul 13 05:00:28 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-ec15dbf3-0db8-4dd1-bf3a-2aa26c29a475 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203969606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2203969 606 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3351243669 |
Short name | T1209 |
Test name | |
Test status | |
Simulation time | 34082565 ps |
CPU time | 0.98 seconds |
Started | Jul 13 05:00:14 PM PDT 24 |
Finished | Jul 13 05:00:15 PM PDT 24 |
Peak memory | 215916 kb |
Host | smart-bbadec51-58a7-4737-80f0-25cc6e42bffb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351243669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3351243 669 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3350261587 |
Short name | T1206 |
Test name | |
Test status | |
Simulation time | 131879386 ps |
CPU time | 2.13 seconds |
Started | Jul 13 05:00:15 PM PDT 24 |
Finished | Jul 13 05:00:17 PM PDT 24 |
Peak memory | 220716 kb |
Host | smart-efcc0049-d74a-4f51-88c6-113e060b4223 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350261587 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3350261587 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2027756824 |
Short name | T1188 |
Test name | |
Test status | |
Simulation time | 28058755 ps |
CPU time | 1.18 seconds |
Started | Jul 13 05:00:11 PM PDT 24 |
Finished | Jul 13 05:00:13 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-b03e3bc9-0d42-4e1c-ab7c-1dea3ded3999 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027756824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2027756824 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_intr_test.726164572 |
Short name | T1095 |
Test name | |
Test status | |
Simulation time | 57255794 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:00:12 PM PDT 24 |
Finished | Jul 13 05:00:13 PM PDT 24 |
Peak memory | 215748 kb |
Host | smart-18901638-73dd-4add-a6e4-8adf14b495ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726164572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.726164572 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2116342445 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 22326194 ps |
CPU time | 1.37 seconds |
Started | Jul 13 05:00:04 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 215800 kb |
Host | smart-3bcdf62c-0907-46cb-a1e6-c0018429fdaf |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116342445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.2116342445 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2606441211 |
Short name | T1202 |
Test name | |
Test status | |
Simulation time | 10842953 ps |
CPU time | 0.75 seconds |
Started | Jul 13 05:00:05 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-6248254c-2406-4785-97fe-23ce7fde5d40 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606441211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2606441211 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1935795774 |
Short name | T1111 |
Test name | |
Test status | |
Simulation time | 90235543 ps |
CPU time | 2.35 seconds |
Started | Jul 13 05:00:10 PM PDT 24 |
Finished | Jul 13 05:00:12 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-3f661e9a-16e1-4dcb-95fb-f17d2b7aad70 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935795774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.1935795774 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3288336911 |
Short name | T1160 |
Test name | |
Test status | |
Simulation time | 63276635 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:00:04 PM PDT 24 |
Finished | Jul 13 05:00:06 PM PDT 24 |
Peak memory | 216332 kb |
Host | smart-95c7b497-58e1-4362-b091-d439e4f16bb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288336911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.3288336911 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3449507836 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 28762228 ps |
CPU time | 1.69 seconds |
Started | Jul 13 05:00:07 PM PDT 24 |
Finished | Jul 13 05:00:09 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-46092905-0891-43bc-9929-c2872633dbd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449507836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.3449507836 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_tl_errors.577319275 |
Short name | T1133 |
Test name | |
Test status | |
Simulation time | 246374867 ps |
CPU time | 1.96 seconds |
Started | Jul 13 05:00:05 PM PDT 24 |
Finished | Jul 13 05:00:07 PM PDT 24 |
Peak memory | 215964 kb |
Host | smart-14c1f273-2693-4ad0-affe-7d7ffd2177fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577319275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.577319275 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2343374215 |
Short name | T1189 |
Test name | |
Test status | |
Simulation time | 266285679 ps |
CPU time | 4.64 seconds |
Started | Jul 13 05:00:05 PM PDT 24 |
Finished | Jul 13 05:00:10 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-cfaffe7a-a4e8-4bbf-8dd3-df7021fd1e0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343374215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.23433 74215 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.kmac_intr_test.1260217775 |
Short name | T1131 |
Test name | |
Test status | |
Simulation time | 28024499 ps |
CPU time | 0.78 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215744 kb |
Host | smart-d95ff86c-728a-4ebd-b9d6-3941d70436c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260217775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1260217775 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.kmac_intr_test.2931466664 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 44492337 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-c1c778d3-65e6-407b-84e7-08dc371186be |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931466664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2931466664 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.kmac_intr_test.3803782200 |
Short name | T1163 |
Test name | |
Test status | |
Simulation time | 24782487 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:01:32 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-5c1c9c80-6e42-4a57-88d3-ed2b636fc80c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803782200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3803782200 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.kmac_intr_test.2854498871 |
Short name | T1174 |
Test name | |
Test status | |
Simulation time | 27831931 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-01bf4f68-ec91-4c5b-9551-0567927afc8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854498871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2854498871 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.kmac_intr_test.3901572560 |
Short name | T1125 |
Test name | |
Test status | |
Simulation time | 13694154 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:33 PM PDT 24 |
Peak memory | 215736 kb |
Host | smart-447626b0-3050-4919-87a1-c0786ad1cf5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901572560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3901572560 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.kmac_intr_test.3299951053 |
Short name | T1086 |
Test name | |
Test status | |
Simulation time | 15299193 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:01:29 PM PDT 24 |
Finished | Jul 13 05:01:31 PM PDT 24 |
Peak memory | 215736 kb |
Host | smart-c6a5838d-4e85-4492-b11b-a544013224c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299951053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3299951053 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.kmac_intr_test.2920762208 |
Short name | T1092 |
Test name | |
Test status | |
Simulation time | 36042669 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:01:30 PM PDT 24 |
Finished | Jul 13 05:01:32 PM PDT 24 |
Peak memory | 215716 kb |
Host | smart-dded827e-4b90-4d54-8b57-5743174f86b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920762208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2920762208 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.kmac_intr_test.3372374179 |
Short name | T1159 |
Test name | |
Test status | |
Simulation time | 39229118 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:01:33 PM PDT 24 |
Finished | Jul 13 05:01:34 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-d49ac45f-672d-4a06-a05c-e3e9ee8c99d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372374179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3372374179 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.kmac_intr_test.1994646158 |
Short name | T1231 |
Test name | |
Test status | |
Simulation time | 15270796 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:01:37 PM PDT 24 |
Finished | Jul 13 05:01:38 PM PDT 24 |
Peak memory | 215776 kb |
Host | smart-f528650c-7cc5-4557-b377-43741a0a1c24 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994646158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1994646158 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.kmac_intr_test.4256324847 |
Short name | T1213 |
Test name | |
Test status | |
Simulation time | 52972099 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:01:36 PM PDT 24 |
Finished | Jul 13 05:01:37 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-ac04a253-eac5-4f45-acc9-8e78429d2c0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256324847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.4256324847 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3204821141 |
Short name | T1155 |
Test name | |
Test status | |
Simulation time | 40190550 ps |
CPU time | 2.44 seconds |
Started | Jul 13 05:00:21 PM PDT 24 |
Finished | Jul 13 05:00:24 PM PDT 24 |
Peak memory | 220708 kb |
Host | smart-26b1582c-e3e1-4288-b6c5-e90e46d4e0f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204821141 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3204821141 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4202786673 |
Short name | T1175 |
Test name | |
Test status | |
Simulation time | 17140946 ps |
CPU time | 1.13 seconds |
Started | Jul 13 05:00:22 PM PDT 24 |
Finished | Jul 13 05:00:23 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-a28626b5-c038-4174-9db4-1b5321b26e16 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202786673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4202786673 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_intr_test.1903569174 |
Short name | T1169 |
Test name | |
Test status | |
Simulation time | 23579605 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:00:21 PM PDT 24 |
Finished | Jul 13 05:00:22 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-39fac503-74fc-4923-b101-a2e1b8914a95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903569174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1903569174 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2113558682 |
Short name | T1078 |
Test name | |
Test status | |
Simulation time | 198942467 ps |
CPU time | 1.62 seconds |
Started | Jul 13 05:00:21 PM PDT 24 |
Finished | Jul 13 05:00:22 PM PDT 24 |
Peak memory | 215788 kb |
Host | smart-f2496aaa-f153-477d-a3b0-0fadc974f998 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113558682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2113558682 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.295463432 |
Short name | T1177 |
Test name | |
Test status | |
Simulation time | 27319868 ps |
CPU time | 1.05 seconds |
Started | Jul 13 05:00:15 PM PDT 24 |
Finished | Jul 13 05:00:17 PM PDT 24 |
Peak memory | 215880 kb |
Host | smart-2e0b4b06-3ab3-45e1-9bd4-8955f3758559 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295463432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e rrors.295463432 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1166778938 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 73989731 ps |
CPU time | 1.98 seconds |
Started | Jul 13 05:00:22 PM PDT 24 |
Finished | Jul 13 05:00:24 PM PDT 24 |
Peak memory | 216472 kb |
Host | smart-9b19faf3-acf2-4f19-8088-4abf2a4519ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166778938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.1166778938 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1365085070 |
Short name | T1123 |
Test name | |
Test status | |
Simulation time | 48207175 ps |
CPU time | 1.75 seconds |
Started | Jul 13 05:00:21 PM PDT 24 |
Finished | Jul 13 05:00:23 PM PDT 24 |
Peak memory | 215888 kb |
Host | smart-0163212b-8025-4c16-9dc1-fcbc490e2e3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365085070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1365085070 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2258466173 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 114877516 ps |
CPU time | 2.42 seconds |
Started | Jul 13 05:00:21 PM PDT 24 |
Finished | Jul 13 05:00:24 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-f6686b8b-abe5-4148-9112-e94fa15c9e72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258466173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.22584 66173 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2511390855 |
Short name | T1156 |
Test name | |
Test status | |
Simulation time | 22550064 ps |
CPU time | 1.5 seconds |
Started | Jul 13 05:00:31 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 218760 kb |
Host | smart-712169d6-7880-4217-972e-3a91c9273b87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511390855 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2511390855 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3459623763 |
Short name | T1082 |
Test name | |
Test status | |
Simulation time | 15634989 ps |
CPU time | 0.96 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:31 PM PDT 24 |
Peak memory | 215676 kb |
Host | smart-2d3790de-2281-47eb-a61e-e62b492f812c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459623763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3459623763 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_intr_test.1902110662 |
Short name | T1195 |
Test name | |
Test status | |
Simulation time | 11819794 ps |
CPU time | 0.77 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:31 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-7fb28ea2-5c75-4115-90ea-5831ee091a55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902110662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1902110662 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2371796036 |
Short name | T1079 |
Test name | |
Test status | |
Simulation time | 50081208 ps |
CPU time | 1.53 seconds |
Started | Jul 13 05:00:31 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 215848 kb |
Host | smart-f2e06215-898d-4adc-83f4-966b022cbf60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371796036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2371796036 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3146531772 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 110313649 ps |
CPU time | 1.19 seconds |
Started | Jul 13 05:00:29 PM PDT 24 |
Finished | Jul 13 05:00:31 PM PDT 24 |
Peak memory | 216208 kb |
Host | smart-1e8175f6-04d5-4682-af99-05e3741157b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146531772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.3146531772 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3867940426 |
Short name | T1083 |
Test name | |
Test status | |
Simulation time | 185585292 ps |
CPU time | 2.63 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 219636 kb |
Host | smart-46220f7d-9cb2-4300-a960-a10fac811285 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867940426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3867940426 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_tl_errors.830882383 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 46732725 ps |
CPU time | 2.97 seconds |
Started | Jul 13 05:00:28 PM PDT 24 |
Finished | Jul 13 05:00:32 PM PDT 24 |
Peak memory | 215924 kb |
Host | smart-6a5ee02e-2d64-47c5-b3d5-924f9049d448 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830882383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.830882383 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.495634602 |
Short name | T1150 |
Test name | |
Test status | |
Simulation time | 115602719 ps |
CPU time | 2.74 seconds |
Started | Jul 13 05:00:29 PM PDT 24 |
Finished | Jul 13 05:00:32 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-7a124109-719b-4b3b-aa54-45ed375a3abb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495634602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.495634 602 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1731766840 |
Short name | T1154 |
Test name | |
Test status | |
Simulation time | 149841163 ps |
CPU time | 2.39 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 220600 kb |
Host | smart-35eb692b-6c81-40a8-8cb3-8ec87b01a01e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731766840 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1731766840 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_csr_rw.385729087 |
Short name | T1207 |
Test name | |
Test status | |
Simulation time | 23816873 ps |
CPU time | 1.01 seconds |
Started | Jul 13 05:00:28 PM PDT 24 |
Finished | Jul 13 05:00:29 PM PDT 24 |
Peak memory | 215676 kb |
Host | smart-7e315e20-7344-4ee8-b908-47b3b4272fc9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385729087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.385729087 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_intr_test.3841117273 |
Short name | T1234 |
Test name | |
Test status | |
Simulation time | 55410897 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:00:31 PM PDT 24 |
Finished | Jul 13 05:00:32 PM PDT 24 |
Peak memory | 215644 kb |
Host | smart-207164eb-a48f-49d0-aa64-cab959cbf5ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841117273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3841117273 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.304533606 |
Short name | T1170 |
Test name | |
Test status | |
Simulation time | 88102085 ps |
CPU time | 2.46 seconds |
Started | Jul 13 05:00:31 PM PDT 24 |
Finished | Jul 13 05:00:34 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-5ae93d52-8482-4482-8e25-10e0ac480e1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304533606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_ outstanding.304533606 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.422011070 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 115275101 ps |
CPU time | 1.19 seconds |
Started | Jul 13 05:00:31 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 216060 kb |
Host | smart-51190816-66de-4002-a57e-7b98dff7b675 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422011070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e rrors.422011070 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1615839728 |
Short name | T1198 |
Test name | |
Test status | |
Simulation time | 439713882 ps |
CPU time | 2.73 seconds |
Started | Jul 13 05:00:32 PM PDT 24 |
Finished | Jul 13 05:00:36 PM PDT 24 |
Peak memory | 218940 kb |
Host | smart-006c9410-db1a-440f-97c3-851ffde46bed |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615839728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.1615839728 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1108368220 |
Short name | T1105 |
Test name | |
Test status | |
Simulation time | 321858033 ps |
CPU time | 2.25 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 215964 kb |
Host | smart-af840cdb-9065-4b92-8bba-e42caba95c24 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108368220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1108368220 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2186165047 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 1356919578 ps |
CPU time | 2.83 seconds |
Started | Jul 13 05:00:30 PM PDT 24 |
Finished | Jul 13 05:00:33 PM PDT 24 |
Peak memory | 215872 kb |
Host | smart-a9df8a20-51c7-41f9-901c-5a8c171fd880 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186165047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.21861 65047 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3751775714 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 46862205 ps |
CPU time | 1.62 seconds |
Started | Jul 13 05:00:36 PM PDT 24 |
Finished | Jul 13 05:00:38 PM PDT 24 |
Peak memory | 218864 kb |
Host | smart-090eb7a7-d713-461c-afc9-69a4fc38f759 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751775714 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3751775714 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2401257094 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 33318422 ps |
CPU time | 1.19 seconds |
Started | Jul 13 05:00:39 PM PDT 24 |
Finished | Jul 13 05:00:41 PM PDT 24 |
Peak memory | 215728 kb |
Host | smart-05411b02-ebf8-42a6-9827-8014a1d1601b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401257094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2401257094 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_intr_test.538695357 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 37323056 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:00:36 PM PDT 24 |
Finished | Jul 13 05:00:38 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-6e4ded0d-ce7e-4877-acd3-05091e00f994 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538695357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.538695357 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1159962062 |
Short name | T1096 |
Test name | |
Test status | |
Simulation time | 193571766 ps |
CPU time | 1.56 seconds |
Started | Jul 13 05:00:39 PM PDT 24 |
Finished | Jul 13 05:00:41 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-65d58c8f-102c-4bd6-b9ca-71dea4660341 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159962062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.1159962062 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.837320750 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 33289772 ps |
CPU time | 1.18 seconds |
Started | Jul 13 05:00:37 PM PDT 24 |
Finished | Jul 13 05:00:39 PM PDT 24 |
Peak memory | 217168 kb |
Host | smart-fe955e01-cdd6-4210-8a99-6fa2be619fef |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837320750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e rrors.837320750 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3636780007 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 79227944 ps |
CPU time | 2.35 seconds |
Started | Jul 13 05:00:36 PM PDT 24 |
Finished | Jul 13 05:00:39 PM PDT 24 |
Peak memory | 219752 kb |
Host | smart-41c6243d-ec8f-46ce-94e0-e1652b11dc91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636780007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.3636780007 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1990668485 |
Short name | T1226 |
Test name | |
Test status | |
Simulation time | 385074548 ps |
CPU time | 3.13 seconds |
Started | Jul 13 05:00:37 PM PDT 24 |
Finished | Jul 13 05:00:40 PM PDT 24 |
Peak memory | 215956 kb |
Host | smart-9ff6bae4-8649-4401-8ca7-12df5cfce9c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990668485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1990668485 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1750077096 |
Short name | T1230 |
Test name | |
Test status | |
Simulation time | 135400434 ps |
CPU time | 4.14 seconds |
Started | Jul 13 05:00:36 PM PDT 24 |
Finished | Jul 13 05:00:41 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-526157a4-aa3e-4990-8a25-e75017598256 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750077096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.17500 77096 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1020017489 |
Short name | T1203 |
Test name | |
Test status | |
Simulation time | 415268496 ps |
CPU time | 1.95 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 217192 kb |
Host | smart-eed25fdf-b370-4185-bc03-739e98de0d88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020017489 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1020017489 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1382241063 |
Short name | T1097 |
Test name | |
Test status | |
Simulation time | 42823910 ps |
CPU time | 0.92 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 215740 kb |
Host | smart-128e116c-fd84-408b-b021-d04052ecf8e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382241063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1382241063 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_intr_test.1296775251 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 15299403 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:00:47 PM PDT 24 |
Finished | Jul 13 05:00:48 PM PDT 24 |
Peak memory | 215760 kb |
Host | smart-4654501d-74c5-43bb-9d19-898e96634e39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296775251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1296775251 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.982177103 |
Short name | T1122 |
Test name | |
Test status | |
Simulation time | 27421278 ps |
CPU time | 1.47 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:50 PM PDT 24 |
Peak memory | 215900 kb |
Host | smart-8739c0a9-3ed8-4e7f-ab3b-b09be3873503 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982177103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_ outstanding.982177103 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1085766096 |
Short name | T1091 |
Test name | |
Test status | |
Simulation time | 51038088 ps |
CPU time | 0.94 seconds |
Started | Jul 13 05:00:37 PM PDT 24 |
Finished | Jul 13 05:00:38 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-bf56449a-c0e6-44e6-a0c0-209628490303 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085766096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.1085766096 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4199509268 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 294203502 ps |
CPU time | 1.97 seconds |
Started | Jul 13 05:00:34 PM PDT 24 |
Finished | Jul 13 05:00:37 PM PDT 24 |
Peak memory | 219088 kb |
Host | smart-f378f8f3-7822-45b8-8b4d-2d02a06d4fa4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199509268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.4199509268 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1149333164 |
Short name | T1127 |
Test name | |
Test status | |
Simulation time | 59156640 ps |
CPU time | 2.24 seconds |
Started | Jul 13 05:00:48 PM PDT 24 |
Finished | Jul 13 05:00:51 PM PDT 24 |
Peak memory | 215956 kb |
Host | smart-1f092d21-6318-44e8-84db-a73a7b1e4aeb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149333164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1149333164 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_tl_errors/latest |
Test location | /workspace/coverage/default/0.kmac_alert_test.1569946365 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 20933412 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:05:22 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-5981dec9-aa39-4f8f-9955-30502402f14c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569946365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1569946365 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_alert_test/latest |
Test location | /workspace/coverage/default/0.kmac_app.2739886015 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 1189502240 ps |
CPU time | 58.63 seconds |
Started | Jul 13 05:05:21 PM PDT 24 |
Finished | Jul 13 05:06:21 PM PDT 24 |
Peak memory | 227852 kb |
Host | smart-5400923a-b5cb-4a74-afa7-b789ab3c0175 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739886015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2739886015 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_app/latest |
Test location | /workspace/coverage/default/0.kmac_app_with_partial_data.561163127 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 80841184406 ps |
CPU time | 439.81 seconds |
Started | Jul 13 05:05:18 PM PDT 24 |
Finished | Jul 13 05:12:39 PM PDT 24 |
Peak memory | 252280 kb |
Host | smart-fc0932f8-0a79-4c6f-85ff-efcb2854e87e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561163127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.561163127 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/0.kmac_burst_write.713848415 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 15870862719 ps |
CPU time | 1462.99 seconds |
Started | Jul 13 05:05:10 PM PDT 24 |
Finished | Jul 13 05:29:33 PM PDT 24 |
Peak memory | 238024 kb |
Host | smart-2bf52bda-8e16-4f3a-b084-f4177454e2a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713848415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.713848415 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_burst_write/latest |
Test location | /workspace/coverage/default/0.kmac_entropy_mode_error.3997359586 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 1388859215 ps |
CPU time | 15.31 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:05:35 PM PDT 24 |
Peak memory | 220896 kb |
Host | smart-f6f87880-e577-4765-95a2-fd96f4814e31 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3997359586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3997359586 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/0.kmac_entropy_ready_error.2425366022 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 32034434895 ps |
CPU time | 42.73 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:06:02 PM PDT 24 |
Peak memory | 226656 kb |
Host | smart-90966d55-4bcf-4d9e-aca8-b49d925c88c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425366022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2425366022 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/0.kmac_entropy_refresh.184914216 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 54248830161 ps |
CPU time | 382.15 seconds |
Started | Jul 13 05:05:18 PM PDT 24 |
Finished | Jul 13 05:11:41 PM PDT 24 |
Peak memory | 252836 kb |
Host | smart-5cb7e1bd-ee60-4ed9-8ada-77798d37d1de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184914216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.184914216 +enable_masking=1 +sw_ key_masked=0 |
Directory | /workspace/0.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/0.kmac_error.616782143 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 72933925671 ps |
CPU time | 436.41 seconds |
Started | Jul 13 05:05:18 PM PDT 24 |
Finished | Jul 13 05:12:35 PM PDT 24 |
Peak memory | 267572 kb |
Host | smart-457d7689-029e-48b4-bc8c-d3ca578527fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616782143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.616782143 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_error/latest |
Test location | /workspace/coverage/default/0.kmac_key_error.2596295887 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 1490797648 ps |
CPU time | 5.68 seconds |
Started | Jul 13 05:05:17 PM PDT 24 |
Finished | Jul 13 05:05:23 PM PDT 24 |
Peak memory | 223028 kb |
Host | smart-f9476750-944e-46e0-9da6-532efa219899 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596295887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2596295887 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_key_error/latest |
Test location | /workspace/coverage/default/0.kmac_lc_escalation.2173854288 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 52898265 ps |
CPU time | 1.2 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:05:22 PM PDT 24 |
Peak memory | 226656 kb |
Host | smart-f1ac1f3e-28f4-4571-8bd5-fa505ab60a9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173854288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2173854288 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/0.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/0.kmac_long_msg_and_output.3168362490 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 141738697947 ps |
CPU time | 2229.82 seconds |
Started | Jul 13 05:05:11 PM PDT 24 |
Finished | Jul 13 05:42:22 PM PDT 24 |
Peak memory | 430084 kb |
Host | smart-b7c5908d-0f1f-479b-b5f1-97fb5c3ee46a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168362490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.3168362490 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/0.kmac_mubi.3108410906 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 10728222775 ps |
CPU time | 222.93 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:09:04 PM PDT 24 |
Peak memory | 244140 kb |
Host | smart-628efcdd-f5a1-476a-95c2-44a0f11fab84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3108410906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3108410906 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_mubi/latest |
Test location | /workspace/coverage/default/0.kmac_sec_cm.705887455 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 52935607116 ps |
CPU time | 65.6 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:06:26 PM PDT 24 |
Peak memory | 265340 kb |
Host | smart-909413eb-2137-42fa-b42f-a594d2d9f250 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705887455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.705887455 +enable_masking =1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_sec_cm/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_kmac.3087767748 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 357857664 ps |
CPU time | 5.62 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:05:25 PM PDT 24 |
Peak memory | 218460 kb |
Host | smart-ddd10ec1-f7fa-439a-99a9-8eeab5daebc1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087767748 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.kmac_test_vectors_kmac.3087767748 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3381695738 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 545283050 ps |
CPU time | 5.71 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:05:27 PM PDT 24 |
Peak memory | 218892 kb |
Host | smart-47d8e469-11af-4d1d-af66-9b4fefd3712c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381695738 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3381695738 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1004989881 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 202600915683 ps |
CPU time | 2285.73 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:43:27 PM PDT 24 |
Peak memory | 397164 kb |
Host | smart-b1322fe6-533a-4861-afdd-676a92cdd6b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1004989881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1004989881 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3304629668 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 155877148812 ps |
CPU time | 2100.06 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:40:20 PM PDT 24 |
Peak memory | 377860 kb |
Host | smart-544c1b6f-8f2b-4ba0-8697-485347ed5da6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3304629668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3304629668 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2801712405 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 247873603579 ps |
CPU time | 1801.08 seconds |
Started | Jul 13 05:05:17 PM PDT 24 |
Finished | Jul 13 05:35:19 PM PDT 24 |
Peak memory | 342544 kb |
Host | smart-fbedd634-3f84-4e2e-8550-9a7ad9974022 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2801712405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2801712405 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_512.698620771 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 11588418835 ps |
CPU time | 1137.03 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:24:18 PM PDT 24 |
Peak memory | 295928 kb |
Host | smart-7023724e-717b-4d25-9b62-73fcf5e79408 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=698620771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.698620771 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_shake_128.889649719 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 3246652032672 ps |
CPU time | 6403.24 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 06:52:04 PM PDT 24 |
Peak memory | 663012 kb |
Host | smart-583ab417-b8a8-498f-b3de-2e0ec2824497 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=889649719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.889649719 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/0.kmac_test_vectors_shake_256.425790045 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 200377565663 ps |
CPU time | 4687.89 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 06:23:29 PM PDT 24 |
Peak memory | 565100 kb |
Host | smart-04e52a2a-c502-489d-b452-ec90c1c1df1d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=425790045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.425790045 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/0.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/1.kmac_app.2726342574 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 15076691644 ps |
CPU time | 86.4 seconds |
Started | Jul 13 05:05:22 PM PDT 24 |
Finished | Jul 13 05:06:49 PM PDT 24 |
Peak memory | 231948 kb |
Host | smart-7f0a9e14-5740-4f7e-ab8a-b679d0a86a44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726342574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2726342574 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_app/latest |
Test location | /workspace/coverage/default/1.kmac_app_with_partial_data.1008877261 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 14944826776 ps |
CPU time | 67.11 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:06:28 PM PDT 24 |
Peak memory | 229536 kb |
Host | smart-8fe74b23-7672-4bfb-bc7a-8ed9146c6e24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008877261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1008877261 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/1.kmac_burst_write.591068565 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 7826848756 ps |
CPU time | 283.13 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:10:03 PM PDT 24 |
Peak memory | 229308 kb |
Host | smart-a50308cc-e487-4772-a92c-3c704add6e36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591068565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.591068565 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_burst_write/latest |
Test location | /workspace/coverage/default/1.kmac_edn_timeout_error.2272226015 |
Short name | T1046 |
Test name | |
Test status | |
Simulation time | 24715785 ps |
CPU time | 0.96 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:05:33 PM PDT 24 |
Peak memory | 218160 kb |
Host | smart-dd2e9464-d82d-4b86-b4bd-7e92b5fce38b |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2272226015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2272226015 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/1.kmac_entropy_ready_error.566219096 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 5728621760 ps |
CPU time | 46.87 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:06:18 PM PDT 24 |
Peak memory | 226700 kb |
Host | smart-1117b7d0-9eac-4555-b5ed-2fc78cefba2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566219096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.566219096 +enable_maskin g=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/1.kmac_entropy_refresh.2086756417 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 11056431322 ps |
CPU time | 163.07 seconds |
Started | Jul 13 05:05:28 PM PDT 24 |
Finished | Jul 13 05:08:11 PM PDT 24 |
Peak memory | 238036 kb |
Host | smart-f7dd73bd-9a4f-433d-a17a-09b66f12da74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086756417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2086756417 +enable_masking=1 +s w_key_masked=0 |
Directory | /workspace/1.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/1.kmac_error.2607018079 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 19143049035 ps |
CPU time | 449 seconds |
Started | Jul 13 05:05:33 PM PDT 24 |
Finished | Jul 13 05:13:02 PM PDT 24 |
Peak memory | 264388 kb |
Host | smart-a46c8d22-a1c9-4add-9c2a-a25da81646c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607018079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2607018079 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_error/latest |
Test location | /workspace/coverage/default/1.kmac_key_error.1775624878 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 3450711359 ps |
CPU time | 12.54 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:05:42 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-a08f9480-ed13-4173-8d31-944258ce12ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775624878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1775624878 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_key_error/latest |
Test location | /workspace/coverage/default/1.kmac_lc_escalation.3570647131 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 862823588 ps |
CPU time | 20.21 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:05:51 PM PDT 24 |
Peak memory | 234976 kb |
Host | smart-c7759b43-dc45-49f9-8aef-cc30662f4dd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570647131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3570647131 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/1.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/1.kmac_long_msg_and_output.1697707083 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 24717586072 ps |
CPU time | 2925.67 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:54:05 PM PDT 24 |
Peak memory | 450656 kb |
Host | smart-98d40b05-5188-47c6-bad8-6a04fbfdb056 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697707083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.1697707083 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/1.kmac_mubi.114270599 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1716557657 ps |
CPU time | 90.73 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:07:01 PM PDT 24 |
Peak memory | 231912 kb |
Host | smart-2a4e983e-820f-40b1-a6b3-0ba4bd6959b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114270599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.114270599 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_mubi/latest |
Test location | /workspace/coverage/default/1.kmac_sec_cm.3859709393 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 6875278078 ps |
CPU time | 115.02 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:07:26 PM PDT 24 |
Peak memory | 294464 kb |
Host | smart-34fbf450-c43a-49cf-8b15-cfbee7d85f09 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859709393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3859709393 +enable_maski ng=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_sec_cm/latest |
Test location | /workspace/coverage/default/1.kmac_sideload.2124713044 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 8621234670 ps |
CPU time | 425.62 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:12:27 PM PDT 24 |
Peak memory | 252264 kb |
Host | smart-0b29fc2f-876b-4651-9b5b-d12b20e79ae4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124713044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2124713044 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_sideload/latest |
Test location | /workspace/coverage/default/1.kmac_smoke.3759605115 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 3542317897 ps |
CPU time | 28.12 seconds |
Started | Jul 13 05:05:19 PM PDT 24 |
Finished | Jul 13 05:05:48 PM PDT 24 |
Peak memory | 222988 kb |
Host | smart-b783e700-4d3a-47d3-b4bf-c4dcf8b74cf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759605115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3759605115 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_smoke/latest |
Test location | /workspace/coverage/default/1.kmac_stress_all.966030683 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 173480949676 ps |
CPU time | 1498.24 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:30:30 PM PDT 24 |
Peak memory | 349816 kb |
Host | smart-93c18101-b3e1-445f-9d47-8f9199cdd8c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=966030683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.966030683 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_stress_all/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_kmac.1323132757 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 732003672 ps |
CPU time | 5.87 seconds |
Started | Jul 13 05:05:21 PM PDT 24 |
Finished | Jul 13 05:05:28 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-d10e6a70-6046-492c-b751-26b57b204112 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323132757 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.kmac_test_vectors_kmac.1323132757 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2445950849 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 257918399 ps |
CPU time | 6.31 seconds |
Started | Jul 13 05:05:21 PM PDT 24 |
Finished | Jul 13 05:05:28 PM PDT 24 |
Peak memory | 218456 kb |
Host | smart-d7309cdd-f259-4421-a3ed-cdcd6bb01b6e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445950849 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2445950849 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1136764861 |
Short name | T1062 |
Test name | |
Test status | |
Simulation time | 119258289536 ps |
CPU time | 2148.4 seconds |
Started | Jul 13 05:05:18 PM PDT 24 |
Finished | Jul 13 05:41:08 PM PDT 24 |
Peak memory | 395528 kb |
Host | smart-79994702-eb45-411e-ab32-bd7ed5861f59 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1136764861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1136764861 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_256.2056159820 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 99796810923 ps |
CPU time | 2283.49 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 05:43:25 PM PDT 24 |
Peak memory | 379820 kb |
Host | smart-d2b1fa9c-5c87-47b9-98c2-f2b06e4b8171 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2056159820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2056159820 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1537880836 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 59018797024 ps |
CPU time | 1446.37 seconds |
Started | Jul 13 05:05:22 PM PDT 24 |
Finished | Jul 13 05:29:29 PM PDT 24 |
Peak memory | 334684 kb |
Host | smart-9627aec0-9492-4d2f-a6ef-b0225d013866 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1537880836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1537880836 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_512.579418927 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 34961598212 ps |
CPU time | 1289.97 seconds |
Started | Jul 13 05:05:21 PM PDT 24 |
Finished | Jul 13 05:26:52 PM PDT 24 |
Peak memory | 300972 kb |
Host | smart-1755c488-14cf-4b35-8660-ba820a827235 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=579418927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.579418927 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_shake_128.3201864239 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 239368280210 ps |
CPU time | 5065.64 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 06:29:48 PM PDT 24 |
Peak memory | 649996 kb |
Host | smart-79bc17a4-8e1e-4309-81a1-f86d1d073d1c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3201864239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3201864239 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/1.kmac_test_vectors_shake_256.3593553942 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 629603968481 ps |
CPU time | 4737.96 seconds |
Started | Jul 13 05:05:20 PM PDT 24 |
Finished | Jul 13 06:24:20 PM PDT 24 |
Peak memory | 574184 kb |
Host | smart-02fd7bbf-eba0-4907-ab02-30d6e581de3b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3593553942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3593553942 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/1.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/10.kmac_alert_test.1433017346 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 13232799 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:09:34 PM PDT 24 |
Finished | Jul 13 05:09:35 PM PDT 24 |
Peak memory | 218196 kb |
Host | smart-816a057b-91ce-41da-b7f6-2fc445c23f43 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433017346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1433017346 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_alert_test/latest |
Test location | /workspace/coverage/default/10.kmac_app.41652833 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 4173616374 ps |
CPU time | 13.23 seconds |
Started | Jul 13 05:09:17 PM PDT 24 |
Finished | Jul 13 05:09:32 PM PDT 24 |
Peak memory | 227680 kb |
Host | smart-892c3c13-86fa-49d9-8e28-948664b70538 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41652833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.41652833 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_app/latest |
Test location | /workspace/coverage/default/10.kmac_burst_write.2136295090 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 26854770731 ps |
CPU time | 63.61 seconds |
Started | Jul 13 05:09:08 PM PDT 24 |
Finished | Jul 13 05:10:12 PM PDT 24 |
Peak memory | 226652 kb |
Host | smart-263783c8-e5d0-491d-8ea8-b0f80fb1aff4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136295090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2136295090 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_burst_write/latest |
Test location | /workspace/coverage/default/10.kmac_edn_timeout_error.407636748 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 32496770 ps |
CPU time | 1.1 seconds |
Started | Jul 13 05:09:24 PM PDT 24 |
Finished | Jul 13 05:09:25 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-8011ea76-923b-4872-bc9b-0439d586bf44 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=407636748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.407636748 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/10.kmac_entropy_mode_error.4064150256 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 90999385 ps |
CPU time | 1.15 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:09:35 PM PDT 24 |
Peak memory | 218220 kb |
Host | smart-74380bd2-67a2-4a8d-9d0a-505fba39b337 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4064150256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4064150256 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/10.kmac_entropy_refresh.1320756544 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 5992585216 ps |
CPU time | 309.19 seconds |
Started | Jul 13 05:09:15 PM PDT 24 |
Finished | Jul 13 05:14:25 PM PDT 24 |
Peak memory | 250824 kb |
Host | smart-c7398ed9-3f4a-4e49-a03f-933d6700caee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320756544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1320756544 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/10.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/10.kmac_error.3723001436 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 24670064933 ps |
CPU time | 392.86 seconds |
Started | Jul 13 05:09:15 PM PDT 24 |
Finished | Jul 13 05:15:48 PM PDT 24 |
Peak memory | 259408 kb |
Host | smart-fd0fb517-553d-4996-8944-21267140deed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723001436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3723001436 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_error/latest |
Test location | /workspace/coverage/default/10.kmac_key_error.1256319236 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 5465231819 ps |
CPU time | 7.62 seconds |
Started | Jul 13 05:09:14 PM PDT 24 |
Finished | Jul 13 05:09:22 PM PDT 24 |
Peak memory | 224460 kb |
Host | smart-098c7f7d-e859-4947-a9b2-bdf9adf7fca5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256319236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1256319236 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_key_error/latest |
Test location | /workspace/coverage/default/10.kmac_lc_escalation.2919308071 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 25610209 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:09:35 PM PDT 24 |
Finished | Jul 13 05:09:37 PM PDT 24 |
Peak memory | 226664 kb |
Host | smart-e91079cc-b39c-46bd-8f4e-82e2ca486498 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919308071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2919308071 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/10.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/10.kmac_long_msg_and_output.2354491257 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 118625575806 ps |
CPU time | 2012.19 seconds |
Started | Jul 13 05:09:08 PM PDT 24 |
Finished | Jul 13 05:42:41 PM PDT 24 |
Peak memory | 393004 kb |
Host | smart-2cbb4944-bf88-479a-9edf-565bb599e3cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354491257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a nd_output.2354491257 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/10.kmac_sideload.2065115598 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 37539008259 ps |
CPU time | 206.94 seconds |
Started | Jul 13 05:09:06 PM PDT 24 |
Finished | Jul 13 05:12:34 PM PDT 24 |
Peak memory | 243056 kb |
Host | smart-b5ea70a9-6913-4f45-b28d-f550a5819fa2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065115598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2065115598 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_sideload/latest |
Test location | /workspace/coverage/default/10.kmac_smoke.4245299686 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 552132712 ps |
CPU time | 1.89 seconds |
Started | Jul 13 05:09:06 PM PDT 24 |
Finished | Jul 13 05:09:09 PM PDT 24 |
Peak memory | 218484 kb |
Host | smart-26ff7668-1359-4fa4-aea5-2ff31fbb32e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245299686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4245299686 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_smoke/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_kmac.1307423146 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 740619511 ps |
CPU time | 6.07 seconds |
Started | Jul 13 05:09:07 PM PDT 24 |
Finished | Jul 13 05:09:13 PM PDT 24 |
Peak memory | 218544 kb |
Host | smart-cc214761-7bf0-4201-870a-51825282efe7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307423146 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.1307423146 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.251594067 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 5512763041 ps |
CPU time | 6.78 seconds |
Started | Jul 13 05:09:07 PM PDT 24 |
Finished | Jul 13 05:09:14 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-9e60cc74-6965-47fd-9eb4-c29fd30f77b1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251594067 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.kmac_test_vectors_kmac_xof.251594067 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_224.1121372082 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 88014107810 ps |
CPU time | 2091.72 seconds |
Started | Jul 13 05:09:06 PM PDT 24 |
Finished | Jul 13 05:43:59 PM PDT 24 |
Peak memory | 395740 kb |
Host | smart-1b176be1-bc88-45ec-b9d1-01e5973ca5e7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1121372082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.1121372082 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_256.3297721784 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 384997071220 ps |
CPU time | 2376.74 seconds |
Started | Jul 13 05:09:07 PM PDT 24 |
Finished | Jul 13 05:48:44 PM PDT 24 |
Peak memory | 393548 kb |
Host | smart-e8172ff0-2f0a-49d6-9d22-48e835ee2699 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3297721784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3297721784 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1442014618 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 58369128362 ps |
CPU time | 1546.28 seconds |
Started | Jul 13 05:09:06 PM PDT 24 |
Finished | Jul 13 05:34:53 PM PDT 24 |
Peak memory | 336236 kb |
Host | smart-b56ea667-bf3f-4969-93c1-4f9e2364e8f6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1442014618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1442014618 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_512.339630611 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 33890260975 ps |
CPU time | 1221.57 seconds |
Started | Jul 13 05:09:06 PM PDT 24 |
Finished | Jul 13 05:29:28 PM PDT 24 |
Peak memory | 301312 kb |
Host | smart-94f2b2fa-415b-4709-a254-b57165502ace |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=339630611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.339630611 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/10.kmac_test_vectors_shake_256.1589803418 |
Short name | T1077 |
Test name | |
Test status | |
Simulation time | 298339124170 ps |
CPU time | 4271.24 seconds |
Started | Jul 13 05:09:05 PM PDT 24 |
Finished | Jul 13 06:20:18 PM PDT 24 |
Peak memory | 571148 kb |
Host | smart-4c5819d9-28bd-4e66-b50b-443aa70b8e27 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1589803418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1589803418 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/10.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/11.kmac_alert_test.3689947871 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 46056193 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:09:50 PM PDT 24 |
Finished | Jul 13 05:09:51 PM PDT 24 |
Peak memory | 218164 kb |
Host | smart-9701be8c-3967-4eef-a212-e7613f6910fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689947871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3689947871 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_alert_test/latest |
Test location | /workspace/coverage/default/11.kmac_app.437927415 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2188190496 ps |
CPU time | 50.36 seconds |
Started | Jul 13 05:09:41 PM PDT 24 |
Finished | Jul 13 05:10:32 PM PDT 24 |
Peak memory | 227096 kb |
Host | smart-6a8cd109-1d26-451a-a78a-77e976fae1ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437927415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.437927415 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_app/latest |
Test location | /workspace/coverage/default/11.kmac_burst_write.3189692974 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 13344052908 ps |
CPU time | 1431.45 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:33:25 PM PDT 24 |
Peak memory | 236684 kb |
Host | smart-d53f21f6-d84b-456e-8786-5264f3953ab6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189692974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3189692974 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_burst_write/latest |
Test location | /workspace/coverage/default/11.kmac_edn_timeout_error.3613686209 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 47625800 ps |
CPU time | 0.98 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:09:42 PM PDT 24 |
Peak memory | 218164 kb |
Host | smart-6dbb01aa-2721-49e8-a68b-4bbb6ee3b33d |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3613686209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3613686209 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/11.kmac_entropy_mode_error.2504793252 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 25041688 ps |
CPU time | 1.17 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:09:42 PM PDT 24 |
Peak memory | 218352 kb |
Host | smart-819bbf40-2922-4a67-99e3-0ac13024739d |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2504793252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2504793252 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/11.kmac_entropy_refresh.99998079 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 4273464095 ps |
CPU time | 47.52 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:10:29 PM PDT 24 |
Peak memory | 235392 kb |
Host | smart-53fcf147-a7a3-4eff-8f78-062439b8a147 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99998079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.99998079 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/11.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/11.kmac_key_error.2279721175 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 5428970314 ps |
CPU time | 10.51 seconds |
Started | Jul 13 05:09:41 PM PDT 24 |
Finished | Jul 13 05:09:52 PM PDT 24 |
Peak memory | 225316 kb |
Host | smart-8ba9749e-fa6e-41f4-b4d1-cc88635e461d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279721175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2279721175 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_key_error/latest |
Test location | /workspace/coverage/default/11.kmac_long_msg_and_output.104219044 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 34138020580 ps |
CPU time | 153.58 seconds |
Started | Jul 13 05:09:32 PM PDT 24 |
Finished | Jul 13 05:12:06 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-559dc33f-66e9-4505-af69-edb9f769c8f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104219044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an d_output.104219044 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/11.kmac_sideload.835249829 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 17735992556 ps |
CPU time | 320.39 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:14:54 PM PDT 24 |
Peak memory | 248772 kb |
Host | smart-13f37342-29f7-43a4-993c-f49c58eb42eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835249829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.835249829 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_sideload/latest |
Test location | /workspace/coverage/default/11.kmac_smoke.2071083746 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 13094145072 ps |
CPU time | 18.83 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:09:53 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-02750de4-52f1-44c4-a4df-d717066237ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071083746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2071083746 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_smoke/latest |
Test location | /workspace/coverage/default/11.kmac_stress_all.2807009384 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 92612066006 ps |
CPU time | 799.72 seconds |
Started | Jul 13 05:09:51 PM PDT 24 |
Finished | Jul 13 05:23:11 PM PDT 24 |
Peak memory | 313396 kb |
Host | smart-5de97125-eecd-42d1-828e-542bc0565e08 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2807009384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2807009384 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_stress_all/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_kmac.950656323 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 210823233 ps |
CPU time | 5.5 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:09:47 PM PDT 24 |
Peak memory | 218532 kb |
Host | smart-74529ece-0114-492d-98cb-3019fc5d2968 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950656323 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.kmac_test_vectors_kmac.950656323 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.483741334 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 116333966 ps |
CPU time | 5.99 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:09:47 PM PDT 24 |
Peak memory | 218424 kb |
Host | smart-37774278-243e-49c6-81d6-bed0ab54aaa0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483741334 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.kmac_test_vectors_kmac_xof.483741334 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2546435072 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 802847150320 ps |
CPU time | 2439.75 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:50:13 PM PDT 24 |
Peak memory | 392680 kb |
Host | smart-2549f1d9-a1cd-4a85-916c-01f0ba1ca2b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2546435072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2546435072 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_256.2062975556 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 37092558359 ps |
CPU time | 1911.33 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:41:26 PM PDT 24 |
Peak memory | 381764 kb |
Host | smart-d370b196-4719-4d19-99fc-5f07df16a555 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2062975556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2062975556 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_384.419439045 |
Short name | T1055 |
Test name | |
Test status | |
Simulation time | 46947881646 ps |
CPU time | 1621.16 seconds |
Started | Jul 13 05:09:33 PM PDT 24 |
Finished | Jul 13 05:36:35 PM PDT 24 |
Peak memory | 337492 kb |
Host | smart-cb02fb3e-ba44-490a-8796-41d60b7423ec |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=419439045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.419439045 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3543753892 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 20652897497 ps |
CPU time | 1106.21 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 05:28:06 PM PDT 24 |
Peak memory | 298344 kb |
Host | smart-bb71bfdd-64c4-48fd-bb9d-567aca9904af |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3543753892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3543753892 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_shake_128.2675148597 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 60016130475 ps |
CPU time | 4818.42 seconds |
Started | Jul 13 05:09:40 PM PDT 24 |
Finished | Jul 13 06:30:00 PM PDT 24 |
Peak memory | 659136 kb |
Host | smart-826a7833-03eb-4608-a84b-7cbf31cebac9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2675148597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2675148597 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/11.kmac_test_vectors_shake_256.3906091266 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 222234201152 ps |
CPU time | 4569.11 seconds |
Started | Jul 13 05:09:41 PM PDT 24 |
Finished | Jul 13 06:25:51 PM PDT 24 |
Peak memory | 566208 kb |
Host | smart-ab42adfe-9125-4e65-8cfe-cbd45d3fd69b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3906091266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.3906091266 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/11.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/12.kmac_alert_test.3464377183 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 19752350 ps |
CPU time | 0.88 seconds |
Started | Jul 13 05:10:17 PM PDT 24 |
Finished | Jul 13 05:10:19 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-88905945-8063-4210-b1f3-da446a56089d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464377183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3464377183 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_alert_test/latest |
Test location | /workspace/coverage/default/12.kmac_app.1212191581 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 10789810976 ps |
CPU time | 260 seconds |
Started | Jul 13 05:10:08 PM PDT 24 |
Finished | Jul 13 05:14:28 PM PDT 24 |
Peak memory | 244588 kb |
Host | smart-fec008e3-f33e-4300-a685-46f41044a069 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212191581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1212191581 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_app/latest |
Test location | /workspace/coverage/default/12.kmac_burst_write.240216899 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 34713886981 ps |
CPU time | 449.98 seconds |
Started | Jul 13 05:09:51 PM PDT 24 |
Finished | Jul 13 05:17:21 PM PDT 24 |
Peak memory | 232512 kb |
Host | smart-a301bd4a-9921-41d1-9264-f3654fa0f77d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240216899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.240216899 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_burst_write/latest |
Test location | /workspace/coverage/default/12.kmac_edn_timeout_error.4265149274 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 6224500270 ps |
CPU time | 37.75 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:10:54 PM PDT 24 |
Peak memory | 227516 kb |
Host | smart-b677d89e-6a3a-4267-95c3-02f31bc0e388 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4265149274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.4265149274 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/12.kmac_entropy_mode_error.1529758537 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 28291445 ps |
CPU time | 1.22 seconds |
Started | Jul 13 05:10:16 PM PDT 24 |
Finished | Jul 13 05:10:18 PM PDT 24 |
Peak memory | 218328 kb |
Host | smart-803d7260-25a2-4364-996a-3a6da7b8b995 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1529758537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1529758537 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/12.kmac_entropy_refresh.427111278 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 17894062806 ps |
CPU time | 374.67 seconds |
Started | Jul 13 05:10:08 PM PDT 24 |
Finished | Jul 13 05:16:23 PM PDT 24 |
Peak memory | 250072 kb |
Host | smart-6e9b3e62-d153-4472-9367-14219a769f52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427111278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.427111278 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/12.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/12.kmac_error.425251109 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 36046404196 ps |
CPU time | 232.84 seconds |
Started | Jul 13 05:10:06 PM PDT 24 |
Finished | Jul 13 05:13:59 PM PDT 24 |
Peak memory | 245480 kb |
Host | smart-8f7b6d4e-443c-4832-894e-f632d2753d04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425251109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.425251109 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_error/latest |
Test location | /workspace/coverage/default/12.kmac_key_error.295035691 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 1878329921 ps |
CPU time | 12.49 seconds |
Started | Jul 13 05:10:17 PM PDT 24 |
Finished | Jul 13 05:10:31 PM PDT 24 |
Peak memory | 224304 kb |
Host | smart-538ddee4-587d-4f41-b9c4-1a89f7cbf921 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295035691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.295035691 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_key_error/latest |
Test location | /workspace/coverage/default/12.kmac_lc_escalation.3948421721 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 120942980 ps |
CPU time | 1.32 seconds |
Started | Jul 13 05:10:18 PM PDT 24 |
Finished | Jul 13 05:10:19 PM PDT 24 |
Peak memory | 226532 kb |
Host | smart-58675e0b-0a49-4f84-80ce-3f23cfaa1b51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948421721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3948421721 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/12.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/12.kmac_long_msg_and_output.2139955905 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 32798225260 ps |
CPU time | 649.97 seconds |
Started | Jul 13 05:09:50 PM PDT 24 |
Finished | Jul 13 05:20:40 PM PDT 24 |
Peak memory | 277352 kb |
Host | smart-d5617695-b959-4af0-a24f-f2961db9efc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139955905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.2139955905 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/12.kmac_sideload.2245432496 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 15891593866 ps |
CPU time | 484.98 seconds |
Started | Jul 13 05:09:49 PM PDT 24 |
Finished | Jul 13 05:17:55 PM PDT 24 |
Peak memory | 255756 kb |
Host | smart-6341e6a0-54b1-4846-8382-e61d9f17b35d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245432496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2245432496 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_sideload/latest |
Test location | /workspace/coverage/default/12.kmac_smoke.844379327 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3818366200 ps |
CPU time | 36.24 seconds |
Started | Jul 13 05:09:50 PM PDT 24 |
Finished | Jul 13 05:10:27 PM PDT 24 |
Peak memory | 226716 kb |
Host | smart-2ceb893e-f898-4682-bd93-1e5307cd93e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844379327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.844379327 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_smoke/latest |
Test location | /workspace/coverage/default/12.kmac_stress_all.737192319 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 24161910556 ps |
CPU time | 625.16 seconds |
Started | Jul 13 05:10:17 PM PDT 24 |
Finished | Jul 13 05:20:42 PM PDT 24 |
Peak memory | 252272 kb |
Host | smart-7262de27-b577-4352-aaae-16a8a4892242 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=737192319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.737192319 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_stress_all/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_kmac.52740188 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 170355189 ps |
CPU time | 5.94 seconds |
Started | Jul 13 05:10:00 PM PDT 24 |
Finished | Jul 13 05:10:06 PM PDT 24 |
Peak memory | 219484 kb |
Host | smart-9035b45d-0628-4d85-9815-4da25a6d7330 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52740188 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.kmac_test_vectors_kmac.52740188 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.3813512927 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 203143768 ps |
CPU time | 6.1 seconds |
Started | Jul 13 05:10:08 PM PDT 24 |
Finished | Jul 13 05:10:14 PM PDT 24 |
Peak memory | 219356 kb |
Host | smart-aed7fb9c-b1e6-4d8c-8c49-9e6b82853e69 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813512927 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.3813512927 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_224.354811662 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 120785427495 ps |
CPU time | 2117.1 seconds |
Started | Jul 13 05:09:50 PM PDT 24 |
Finished | Jul 13 05:45:08 PM PDT 24 |
Peak memory | 397580 kb |
Host | smart-1257a439-7f5f-46bd-9d49-2d45a215505d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=354811662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.354811662 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1328953978 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 20196561898 ps |
CPU time | 1890.07 seconds |
Started | Jul 13 05:09:49 PM PDT 24 |
Finished | Jul 13 05:41:19 PM PDT 24 |
Peak memory | 387348 kb |
Host | smart-bbb0aa41-3d5d-423c-8a55-9a5a5f3b04b6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1328953978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1328953978 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_384.3452163030 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 59212309683 ps |
CPU time | 1460.42 seconds |
Started | Jul 13 05:09:58 PM PDT 24 |
Finished | Jul 13 05:34:18 PM PDT 24 |
Peak memory | 339756 kb |
Host | smart-7b3d5506-990f-48ea-8e49-2e7662bad678 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3452163030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3452163030 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_512.2495412624 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 33280021338 ps |
CPU time | 1213.88 seconds |
Started | Jul 13 05:10:00 PM PDT 24 |
Finished | Jul 13 05:30:14 PM PDT 24 |
Peak memory | 298884 kb |
Host | smart-396da300-ad9a-4369-9dad-2cfcd8d00c6b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2495412624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2495412624 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_shake_128.3352653343 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 472795811557 ps |
CPU time | 5941.52 seconds |
Started | Jul 13 05:10:00 PM PDT 24 |
Finished | Jul 13 06:49:02 PM PDT 24 |
Peak memory | 663104 kb |
Host | smart-8e5221bf-5482-4047-acce-82d266423621 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3352653343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.3352653343 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/12.kmac_test_vectors_shake_256.2713972802 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 53860228730 ps |
CPU time | 4347.28 seconds |
Started | Jul 13 05:09:58 PM PDT 24 |
Finished | Jul 13 06:22:26 PM PDT 24 |
Peak memory | 570052 kb |
Host | smart-753e1fc8-d5f0-4f56-89b8-e10e56331a98 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2713972802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2713972802 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/12.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/13.kmac_alert_test.566829174 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 15546210 ps |
CPU time | 0.76 seconds |
Started | Jul 13 05:10:31 PM PDT 24 |
Finished | Jul 13 05:10:32 PM PDT 24 |
Peak memory | 218276 kb |
Host | smart-589c6e1f-4144-458f-8df1-b88d81625807 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566829174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.566829174 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_alert_test/latest |
Test location | /workspace/coverage/default/13.kmac_app.543440092 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 5116167200 ps |
CPU time | 307.55 seconds |
Started | Jul 13 05:10:26 PM PDT 24 |
Finished | Jul 13 05:15:34 PM PDT 24 |
Peak memory | 248596 kb |
Host | smart-edb89fe8-21ae-44ff-b2c6-948d9357d8c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543440092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.543440092 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_app/latest |
Test location | /workspace/coverage/default/13.kmac_burst_write.2097517659 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 15770108673 ps |
CPU time | 390.84 seconds |
Started | Jul 13 05:10:17 PM PDT 24 |
Finished | Jul 13 05:16:48 PM PDT 24 |
Peak memory | 231356 kb |
Host | smart-5039378e-8b31-42ca-97e8-59d7473cc42a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097517659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2097517659 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_burst_write/latest |
Test location | /workspace/coverage/default/13.kmac_edn_timeout_error.228508630 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 323316293 ps |
CPU time | 4.39 seconds |
Started | Jul 13 05:10:34 PM PDT 24 |
Finished | Jul 13 05:10:38 PM PDT 24 |
Peak memory | 218360 kb |
Host | smart-23834cd9-4573-40ef-9244-b5d70eaa4bdb |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=228508630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.228508630 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/13.kmac_entropy_mode_error.1777801709 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 25958749 ps |
CPU time | 1.2 seconds |
Started | Jul 13 05:10:32 PM PDT 24 |
Finished | Jul 13 05:10:33 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-56db836d-e69c-48a0-832e-bd80328dd486 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1777801709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1777801709 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/13.kmac_entropy_refresh.3314707577 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 15652841882 ps |
CPU time | 338.47 seconds |
Started | Jul 13 05:10:24 PM PDT 24 |
Finished | Jul 13 05:16:03 PM PDT 24 |
Peak memory | 248404 kb |
Host | smart-fe212c20-acf0-4915-ae04-6c0158bc4146 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314707577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3314707577 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/13.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/13.kmac_error.1502266615 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 32043672652 ps |
CPU time | 399.29 seconds |
Started | Jul 13 05:10:25 PM PDT 24 |
Finished | Jul 13 05:17:04 PM PDT 24 |
Peak memory | 259332 kb |
Host | smart-eff7c439-ea58-4ecd-bcdf-f2c9770c3af9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502266615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1502266615 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_error/latest |
Test location | /workspace/coverage/default/13.kmac_lc_escalation.173892119 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 129345778 ps |
CPU time | 1.24 seconds |
Started | Jul 13 05:10:31 PM PDT 24 |
Finished | Jul 13 05:10:32 PM PDT 24 |
Peak memory | 226516 kb |
Host | smart-23058b1d-fc2e-4a5c-869e-39d76c4e184f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173892119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.173892119 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/13.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/13.kmac_long_msg_and_output.368830746 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 30021351444 ps |
CPU time | 2759.67 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:56:16 PM PDT 24 |
Peak memory | 455420 kb |
Host | smart-ea42cb98-b67f-4096-aee0-ce40d41f3979 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368830746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an d_output.368830746 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/13.kmac_sideload.2089722377 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 15280538124 ps |
CPU time | 323.16 seconds |
Started | Jul 13 05:10:18 PM PDT 24 |
Finished | Jul 13 05:15:41 PM PDT 24 |
Peak memory | 246980 kb |
Host | smart-202609c4-52c7-42ed-ba10-a343645dfd81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089722377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2089722377 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_sideload/latest |
Test location | /workspace/coverage/default/13.kmac_smoke.4272331484 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 1964501708 ps |
CPU time | 13.58 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:10:29 PM PDT 24 |
Peak memory | 223240 kb |
Host | smart-cc8cc415-8ae0-43a0-8bee-6c32448a7970 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272331484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.4272331484 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_smoke/latest |
Test location | /workspace/coverage/default/13.kmac_stress_all.4074901251 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 52160343524 ps |
CPU time | 1201.84 seconds |
Started | Jul 13 05:10:32 PM PDT 24 |
Finished | Jul 13 05:30:34 PM PDT 24 |
Peak memory | 357204 kb |
Host | smart-746d2a51-0556-48d4-a6d6-bef66ee0670e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4074901251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4074901251 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_stress_all/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_kmac.1183498030 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 873633561 ps |
CPU time | 5.96 seconds |
Started | Jul 13 05:10:23 PM PDT 24 |
Finished | Jul 13 05:10:30 PM PDT 24 |
Peak memory | 218556 kb |
Host | smart-9a0acf72-d22a-43bc-9c83-b67a2f7e45bf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183498030 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.kmac_test_vectors_kmac.1183498030 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2273834803 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 875006319 ps |
CPU time | 6.68 seconds |
Started | Jul 13 05:10:25 PM PDT 24 |
Finished | Jul 13 05:10:32 PM PDT 24 |
Peak memory | 218400 kb |
Host | smart-a4d5e27f-d4ce-496e-9d0a-a5139b958752 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273834803 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2273834803 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_224.3627416430 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 80458066574 ps |
CPU time | 2009.21 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:43:44 PM PDT 24 |
Peak memory | 392148 kb |
Host | smart-1dd02422-a127-4a1a-85b4-7869d9b96eff |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3627416430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.3627416430 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1913921471 |
Short name | T1041 |
Test name | |
Test status | |
Simulation time | 257845236716 ps |
CPU time | 2179.07 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:46:35 PM PDT 24 |
Peak memory | 386432 kb |
Host | smart-0804a74e-5a7c-4196-ae8d-e34832bbfd4a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1913921471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1913921471 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2225836576 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 95297983003 ps |
CPU time | 1729.55 seconds |
Started | Jul 13 05:10:15 PM PDT 24 |
Finished | Jul 13 05:39:05 PM PDT 24 |
Peak memory | 335344 kb |
Host | smart-6dae2dd7-2430-4a89-b9f1-22969db51317 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2225836576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2225836576 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_512.3133932483 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 45066015164 ps |
CPU time | 1221.55 seconds |
Started | Jul 13 05:10:26 PM PDT 24 |
Finished | Jul 13 05:30:48 PM PDT 24 |
Peak memory | 305472 kb |
Host | smart-abeb438a-044c-4f2e-ba36-b82491bb5fa2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3133932483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3133932483 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_shake_128.1294258488 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 120580986598 ps |
CPU time | 5184.35 seconds |
Started | Jul 13 05:10:26 PM PDT 24 |
Finished | Jul 13 06:36:51 PM PDT 24 |
Peak memory | 665956 kb |
Host | smart-807b741a-5772-49f2-9fa6-23912cfd8f8e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1294258488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1294258488 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/13.kmac_test_vectors_shake_256.3554248771 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 224903195693 ps |
CPU time | 4386.67 seconds |
Started | Jul 13 05:10:24 PM PDT 24 |
Finished | Jul 13 06:23:31 PM PDT 24 |
Peak memory | 574900 kb |
Host | smart-69f30e1b-ae52-4f88-a8e6-abe8650dcce4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3554248771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3554248771 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/13.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/14.kmac_alert_test.4040759448 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 38223519 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:10:59 PM PDT 24 |
Finished | Jul 13 05:11:00 PM PDT 24 |
Peak memory | 218244 kb |
Host | smart-8af80a40-32ed-46a3-b6c2-9b54c7b4eb55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040759448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4040759448 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_alert_test/latest |
Test location | /workspace/coverage/default/14.kmac_app.2572606464 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 9592786828 ps |
CPU time | 286.94 seconds |
Started | Jul 13 05:10:50 PM PDT 24 |
Finished | Jul 13 05:15:37 PM PDT 24 |
Peak memory | 247312 kb |
Host | smart-54948f33-3e31-4e5b-8008-be4f41970723 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572606464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2572606464 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_app/latest |
Test location | /workspace/coverage/default/14.kmac_burst_write.2298089548 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 18253308313 ps |
CPU time | 734.62 seconds |
Started | Jul 13 05:10:39 PM PDT 24 |
Finished | Jul 13 05:22:54 PM PDT 24 |
Peak memory | 235000 kb |
Host | smart-ce86d5b7-d005-4b22-9f13-a07e6d0f1d8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298089548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2298089548 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_burst_write/latest |
Test location | /workspace/coverage/default/14.kmac_edn_timeout_error.2902268082 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 512791550 ps |
CPU time | 17.2 seconds |
Started | Jul 13 05:10:58 PM PDT 24 |
Finished | Jul 13 05:11:15 PM PDT 24 |
Peak memory | 229948 kb |
Host | smart-41d93780-fbdc-43fd-b216-ec8f1fbcdfee |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2902268082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2902268082 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/14.kmac_entropy_mode_error.369883762 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 21456199 ps |
CPU time | 1.07 seconds |
Started | Jul 13 05:10:58 PM PDT 24 |
Finished | Jul 13 05:10:59 PM PDT 24 |
Peak memory | 218272 kb |
Host | smart-a70fd9ad-7c98-460c-98fd-ddd606ed703f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=369883762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.369883762 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/14.kmac_entropy_refresh.2461021268 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 8345403847 ps |
CPU time | 325.33 seconds |
Started | Jul 13 05:10:54 PM PDT 24 |
Finished | Jul 13 05:16:19 PM PDT 24 |
Peak memory | 248932 kb |
Host | smart-00178458-485a-4c37-b3af-54ea62fb1993 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461021268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2461021268 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/14.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/14.kmac_error.739058582 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 60342333243 ps |
CPU time | 464.4 seconds |
Started | Jul 13 05:10:51 PM PDT 24 |
Finished | Jul 13 05:18:36 PM PDT 24 |
Peak memory | 269592 kb |
Host | smart-54d8fac2-fc8f-4a00-b71a-f40e7c91bda7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739058582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.739058582 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_error/latest |
Test location | /workspace/coverage/default/14.kmac_key_error.3288306390 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 654748153 ps |
CPU time | 5.28 seconds |
Started | Jul 13 05:10:59 PM PDT 24 |
Finished | Jul 13 05:11:04 PM PDT 24 |
Peak memory | 222924 kb |
Host | smart-19878846-ddc0-4e67-bc2b-6075d25bb11a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288306390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3288306390 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_key_error/latest |
Test location | /workspace/coverage/default/14.kmac_lc_escalation.473750038 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 149361740 ps |
CPU time | 1.42 seconds |
Started | Jul 13 05:10:58 PM PDT 24 |
Finished | Jul 13 05:11:00 PM PDT 24 |
Peak memory | 226612 kb |
Host | smart-017a468a-9f7b-4a07-9097-535b0404732f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473750038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.473750038 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/14.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/14.kmac_long_msg_and_output.1463879818 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 55429983204 ps |
CPU time | 1369.91 seconds |
Started | Jul 13 05:10:34 PM PDT 24 |
Finished | Jul 13 05:33:24 PM PDT 24 |
Peak memory | 345600 kb |
Host | smart-b3884bd4-18e9-49a4-b657-61aa4c27fd26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463879818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.1463879818 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/14.kmac_sideload.1980385534 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 75788100816 ps |
CPU time | 447.25 seconds |
Started | Jul 13 05:10:40 PM PDT 24 |
Finished | Jul 13 05:18:07 PM PDT 24 |
Peak memory | 252796 kb |
Host | smart-dc0ef16f-4aea-49ea-a764-edb9aca2aa89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980385534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1980385534 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_sideload/latest |
Test location | /workspace/coverage/default/14.kmac_smoke.2942179398 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 771742553 ps |
CPU time | 5.37 seconds |
Started | Jul 13 05:10:31 PM PDT 24 |
Finished | Jul 13 05:10:36 PM PDT 24 |
Peak memory | 226340 kb |
Host | smart-002e2975-dae6-4497-a9d3-7a411ceeaa51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942179398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2942179398 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_smoke/latest |
Test location | /workspace/coverage/default/14.kmac_stress_all.825465754 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 125282528214 ps |
CPU time | 2868.17 seconds |
Started | Jul 13 05:10:58 PM PDT 24 |
Finished | Jul 13 05:58:47 PM PDT 24 |
Peak memory | 490120 kb |
Host | smart-851adca0-9f7f-419b-b497-f333b0dc1e80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=825465754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.825465754 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_stress_all/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_kmac.1823081447 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 1171123331 ps |
CPU time | 6.21 seconds |
Started | Jul 13 05:10:50 PM PDT 24 |
Finished | Jul 13 05:10:57 PM PDT 24 |
Peak memory | 218564 kb |
Host | smart-406b0efb-2783-4d83-8719-cb9f8de8eb5c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823081447 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.1823081447 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1845978517 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 1028937452 ps |
CPU time | 6.33 seconds |
Started | Jul 13 05:10:51 PM PDT 24 |
Finished | Jul 13 05:10:57 PM PDT 24 |
Peak memory | 218428 kb |
Host | smart-5a259bad-4dfb-4deb-bfa7-b82eb883a877 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845978517 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1845978517 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2946742532 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 90936710312 ps |
CPU time | 2155.12 seconds |
Started | Jul 13 05:10:42 PM PDT 24 |
Finished | Jul 13 05:46:37 PM PDT 24 |
Peak memory | 391412 kb |
Host | smart-1ea853a5-c0e7-4911-9873-864e2e7784d9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2946742532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2946742532 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_256.3542453803 |
Short name | T1058 |
Test name | |
Test status | |
Simulation time | 179185048611 ps |
CPU time | 2205.41 seconds |
Started | Jul 13 05:10:39 PM PDT 24 |
Finished | Jul 13 05:47:25 PM PDT 24 |
Peak memory | 379180 kb |
Host | smart-e21ec93e-1305-43b9-9ed0-84d104af244a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3542453803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.3542453803 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1419325672 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 214583402089 ps |
CPU time | 1509.83 seconds |
Started | Jul 13 05:10:40 PM PDT 24 |
Finished | Jul 13 05:35:50 PM PDT 24 |
Peak memory | 337936 kb |
Host | smart-6d7aa7a5-5352-4175-a82a-24aec3bfdf33 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1419325672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1419325672 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_512.1360620439 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 193099215585 ps |
CPU time | 1186.55 seconds |
Started | Jul 13 05:10:40 PM PDT 24 |
Finished | Jul 13 05:30:27 PM PDT 24 |
Peak memory | 298744 kb |
Host | smart-4f6c866c-29ee-495a-8b75-894d0922d5ea |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1360620439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1360620439 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_shake_128.3528084908 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 738195328051 ps |
CPU time | 5942.35 seconds |
Started | Jul 13 05:10:54 PM PDT 24 |
Finished | Jul 13 06:49:57 PM PDT 24 |
Peak memory | 654928 kb |
Host | smart-17a36c44-fe8a-4a50-a4cd-42d82f6f0681 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3528084908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3528084908 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/14.kmac_test_vectors_shake_256.137981141 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 186116690277 ps |
CPU time | 4216.66 seconds |
Started | Jul 13 05:10:50 PM PDT 24 |
Finished | Jul 13 06:21:07 PM PDT 24 |
Peak memory | 571996 kb |
Host | smart-72348cb3-f3d2-45dd-bc10-b7e266ffd21e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=137981141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.137981141 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/14.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/15.kmac_alert_test.3888648008 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 47167589 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:11:29 PM PDT 24 |
Finished | Jul 13 05:11:30 PM PDT 24 |
Peak memory | 218200 kb |
Host | smart-af52b6c6-2783-4bea-a096-7aa032701c18 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888648008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3888648008 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_alert_test/latest |
Test location | /workspace/coverage/default/15.kmac_app.2213589294 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 25783366260 ps |
CPU time | 175.23 seconds |
Started | Jul 13 05:11:13 PM PDT 24 |
Finished | Jul 13 05:14:09 PM PDT 24 |
Peak memory | 238764 kb |
Host | smart-24e629f1-9d61-4a8a-8538-bbffd6f0bf29 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213589294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2213589294 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_app/latest |
Test location | /workspace/coverage/default/15.kmac_burst_write.2181537530 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 15283630100 ps |
CPU time | 747.55 seconds |
Started | Jul 13 05:11:04 PM PDT 24 |
Finished | Jul 13 05:23:32 PM PDT 24 |
Peak memory | 235140 kb |
Host | smart-22fb64dd-0424-443f-a826-c4ab3045dae8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181537530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2181537530 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_burst_write/latest |
Test location | /workspace/coverage/default/15.kmac_edn_timeout_error.3499718897 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 19992830 ps |
CPU time | 0.98 seconds |
Started | Jul 13 05:11:13 PM PDT 24 |
Finished | Jul 13 05:11:14 PM PDT 24 |
Peak memory | 218160 kb |
Host | smart-795d6fab-5bb4-48bb-b8b2-105cd6c8908a |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3499718897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3499718897 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/15.kmac_entropy_mode_error.121954698 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 102963991 ps |
CPU time | 1.03 seconds |
Started | Jul 13 05:11:22 PM PDT 24 |
Finished | Jul 13 05:11:23 PM PDT 24 |
Peak memory | 218160 kb |
Host | smart-fd6cd695-3714-410d-9463-be4cd2fb44e4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=121954698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.121954698 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/15.kmac_entropy_refresh.3893150107 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 1751975914 ps |
CPU time | 20.69 seconds |
Started | Jul 13 05:11:14 PM PDT 24 |
Finished | Jul 13 05:11:35 PM PDT 24 |
Peak memory | 226604 kb |
Host | smart-7342e475-add1-4ec5-9d80-f40d1ab2f3ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893150107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3893150107 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/15.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/15.kmac_error.1298998608 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 5811490202 ps |
CPU time | 447.24 seconds |
Started | Jul 13 05:11:13 PM PDT 24 |
Finished | Jul 13 05:18:41 PM PDT 24 |
Peak memory | 271816 kb |
Host | smart-b4ae437a-8699-4db0-83ac-d79e9b97c553 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298998608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1298998608 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_error/latest |
Test location | /workspace/coverage/default/15.kmac_key_error.2529429439 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 879605285 ps |
CPU time | 4.24 seconds |
Started | Jul 13 05:11:12 PM PDT 24 |
Finished | Jul 13 05:11:17 PM PDT 24 |
Peak memory | 222948 kb |
Host | smart-ed60c709-4838-41b0-a434-b1156b7367cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529429439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2529429439 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_key_error/latest |
Test location | /workspace/coverage/default/15.kmac_lc_escalation.3391030111 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 35423669 ps |
CPU time | 1.3 seconds |
Started | Jul 13 05:11:28 PM PDT 24 |
Finished | Jul 13 05:11:30 PM PDT 24 |
Peak memory | 226552 kb |
Host | smart-64bd2272-7925-4962-97c6-7bc98a46238f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391030111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3391030111 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/15.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/15.kmac_long_msg_and_output.472380783 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 234758086603 ps |
CPU time | 1416.07 seconds |
Started | Jul 13 05:11:03 PM PDT 24 |
Finished | Jul 13 05:34:40 PM PDT 24 |
Peak memory | 320504 kb |
Host | smart-84184599-454e-4703-87e2-9e77578fae92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472380783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an d_output.472380783 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/15.kmac_sideload.1195761683 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 14054037194 ps |
CPU time | 166.64 seconds |
Started | Jul 13 05:11:05 PM PDT 24 |
Finished | Jul 13 05:13:52 PM PDT 24 |
Peak memory | 237028 kb |
Host | smart-0b77d90e-3619-4223-9f38-f430f7fc5302 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195761683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1195761683 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_sideload/latest |
Test location | /workspace/coverage/default/15.kmac_smoke.2475844018 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 3650748362 ps |
CPU time | 84.86 seconds |
Started | Jul 13 05:11:05 PM PDT 24 |
Finished | Jul 13 05:12:30 PM PDT 24 |
Peak memory | 221440 kb |
Host | smart-c0ecc296-cb46-454a-beda-e43aac52eba6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475844018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2475844018 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_smoke/latest |
Test location | /workspace/coverage/default/15.kmac_stress_all.2578472242 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 214348911954 ps |
CPU time | 1572.3 seconds |
Started | Jul 13 05:11:28 PM PDT 24 |
Finished | Jul 13 05:37:41 PM PDT 24 |
Peak memory | 357804 kb |
Host | smart-0e964311-6c2d-4cdb-abeb-de8e38f2a275 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2578472242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2578472242 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_stress_all/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_kmac.252580942 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 822541032 ps |
CPU time | 6.55 seconds |
Started | Jul 13 05:11:12 PM PDT 24 |
Finished | Jul 13 05:11:19 PM PDT 24 |
Peak memory | 219508 kb |
Host | smart-111f3c1a-6158-4739-8b22-bdaabc07f794 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252580942 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.kmac_test_vectors_kmac.252580942 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.2343640777 |
Short name | T1048 |
Test name | |
Test status | |
Simulation time | 100020130 ps |
CPU time | 6.11 seconds |
Started | Jul 13 05:11:13 PM PDT 24 |
Finished | Jul 13 05:11:20 PM PDT 24 |
Peak memory | 219356 kb |
Host | smart-9e305c4a-58f7-43e2-8898-72d393b7a315 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343640777 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.2343640777 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_224.1704647943 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 64704386680 ps |
CPU time | 2169.18 seconds |
Started | Jul 13 05:11:06 PM PDT 24 |
Finished | Jul 13 05:47:16 PM PDT 24 |
Peak memory | 390052 kb |
Host | smart-34aa9c11-433e-46d2-89b0-16208c777138 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1704647943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1704647943 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_256.595488883 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 265044720609 ps |
CPU time | 2114.32 seconds |
Started | Jul 13 05:11:06 PM PDT 24 |
Finished | Jul 13 05:46:21 PM PDT 24 |
Peak memory | 380856 kb |
Host | smart-7be393f2-974c-40da-a5a6-2bf1cfb5c549 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=595488883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.595488883 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_384.723440635 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 195114188821 ps |
CPU time | 1538.08 seconds |
Started | Jul 13 05:11:06 PM PDT 24 |
Finished | Jul 13 05:36:45 PM PDT 24 |
Peak memory | 336056 kb |
Host | smart-f718c7b1-c392-41e3-aca5-1928ebfe49ee |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=723440635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.723440635 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2224152319 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 421156214986 ps |
CPU time | 1330.26 seconds |
Started | Jul 13 05:11:03 PM PDT 24 |
Finished | Jul 13 05:33:14 PM PDT 24 |
Peak memory | 296640 kb |
Host | smart-593a841b-abd0-43a6-9f30-32cbe7db5931 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2224152319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2224152319 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_shake_128.3120689784 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 540983930219 ps |
CPU time | 6189.44 seconds |
Started | Jul 13 05:11:13 PM PDT 24 |
Finished | Jul 13 06:54:24 PM PDT 24 |
Peak memory | 669352 kb |
Host | smart-26508319-3788-4438-bc20-5787df0afd21 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3120689784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3120689784 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/15.kmac_test_vectors_shake_256.2789658048 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 216319916233 ps |
CPU time | 4502.6 seconds |
Started | Jul 13 05:11:14 PM PDT 24 |
Finished | Jul 13 06:26:18 PM PDT 24 |
Peak memory | 563652 kb |
Host | smart-f14bba83-8f2c-48c1-a880-68db9214d9fa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2789658048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2789658048 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/15.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/16.kmac_alert_test.660099833 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 19300952 ps |
CPU time | 0.9 seconds |
Started | Jul 13 05:12:01 PM PDT 24 |
Finished | Jul 13 05:12:02 PM PDT 24 |
Peak memory | 218184 kb |
Host | smart-a8428620-8f15-44b0-8c58-01e7e81b5cf5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660099833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.660099833 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_alert_test/latest |
Test location | /workspace/coverage/default/16.kmac_app.3607918266 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 12834794757 ps |
CPU time | 240.22 seconds |
Started | Jul 13 05:11:53 PM PDT 24 |
Finished | Jul 13 05:15:54 PM PDT 24 |
Peak memory | 243460 kb |
Host | smart-e1e7fcd0-fba4-4da7-83c9-f56f4a6e290a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607918266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3607918266 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_app/latest |
Test location | /workspace/coverage/default/16.kmac_burst_write.1183948453 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 2974980294 ps |
CPU time | 288.95 seconds |
Started | Jul 13 05:11:36 PM PDT 24 |
Finished | Jul 13 05:16:25 PM PDT 24 |
Peak memory | 229108 kb |
Host | smart-559eb3b8-896a-4898-a422-67e43c2ec1a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183948453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1183948453 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_burst_write/latest |
Test location | /workspace/coverage/default/16.kmac_edn_timeout_error.753796848 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 18923585 ps |
CPU time | 1.06 seconds |
Started | Jul 13 05:12:01 PM PDT 24 |
Finished | Jul 13 05:12:03 PM PDT 24 |
Peak memory | 218272 kb |
Host | smart-76cd2853-f10b-4af4-9e64-e8c5e9df8ea4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=753796848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.753796848 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/16.kmac_entropy_mode_error.1322278679 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 52849250 ps |
CPU time | 0.99 seconds |
Started | Jul 13 05:12:01 PM PDT 24 |
Finished | Jul 13 05:12:02 PM PDT 24 |
Peak memory | 218036 kb |
Host | smart-77fa1fe5-082f-4d19-94a2-9313705a5a39 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1322278679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1322278679 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/16.kmac_entropy_refresh.2566599511 |
Short name | T1049 |
Test name | |
Test status | |
Simulation time | 10616885805 ps |
CPU time | 128.5 seconds |
Started | Jul 13 05:11:52 PM PDT 24 |
Finished | Jul 13 05:14:01 PM PDT 24 |
Peak memory | 236524 kb |
Host | smart-a7ad0019-40a5-4c0b-a9b4-e157b00acdd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566599511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2566599511 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/16.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/16.kmac_error.4015993446 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 8572370517 ps |
CPU time | 211.14 seconds |
Started | Jul 13 05:11:53 PM PDT 24 |
Finished | Jul 13 05:15:24 PM PDT 24 |
Peak memory | 259428 kb |
Host | smart-d9572429-0d56-4a9e-a560-406c44b31a8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015993446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.4015993446 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_error/latest |
Test location | /workspace/coverage/default/16.kmac_key_error.2526052302 |
Short name | T1067 |
Test name | |
Test status | |
Simulation time | 328254335 ps |
CPU time | 2.74 seconds |
Started | Jul 13 05:12:00 PM PDT 24 |
Finished | Jul 13 05:12:03 PM PDT 24 |
Peak memory | 222744 kb |
Host | smart-1327ae62-7137-4c62-8928-f8c63035af07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526052302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2526052302 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_key_error/latest |
Test location | /workspace/coverage/default/16.kmac_long_msg_and_output.2027158244 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 963510014170 ps |
CPU time | 3345.99 seconds |
Started | Jul 13 05:11:36 PM PDT 24 |
Finished | Jul 13 06:07:23 PM PDT 24 |
Peak memory | 454816 kb |
Host | smart-b4b7b0f7-f45d-4d63-a9ac-07bfe813cd4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027158244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.2027158244 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/16.kmac_sideload.3339325097 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 421252213 ps |
CPU time | 36.01 seconds |
Started | Jul 13 05:11:35 PM PDT 24 |
Finished | Jul 13 05:12:12 PM PDT 24 |
Peak memory | 226620 kb |
Host | smart-a6285dc1-aea3-44c7-adeb-24b04b0a9e64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339325097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3339325097 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_sideload/latest |
Test location | /workspace/coverage/default/16.kmac_smoke.2410373708 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 4016242515 ps |
CPU time | 65.45 seconds |
Started | Jul 13 05:11:28 PM PDT 24 |
Finished | Jul 13 05:12:34 PM PDT 24 |
Peak memory | 226660 kb |
Host | smart-5ad4b13c-3ce4-47d6-a593-71ce2c792004 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410373708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2410373708 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_smoke/latest |
Test location | /workspace/coverage/default/16.kmac_stress_all.1453323601 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 7009852302 ps |
CPU time | 87.03 seconds |
Started | Jul 13 05:12:01 PM PDT 24 |
Finished | Jul 13 05:13:28 PM PDT 24 |
Peak memory | 240236 kb |
Host | smart-fb1fa86c-8d3c-42c1-ba3e-abf22b7ece36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1453323601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1453323601 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_stress_all/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_kmac.1200448223 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 117989846 ps |
CPU time | 6.19 seconds |
Started | Jul 13 05:11:45 PM PDT 24 |
Finished | Jul 13 05:11:52 PM PDT 24 |
Peak memory | 218564 kb |
Host | smart-907d050a-2459-414d-a462-ef561f5e7a07 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200448223 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.kmac_test_vectors_kmac.1200448223 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3877426911 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 229550809 ps |
CPU time | 5.27 seconds |
Started | Jul 13 05:11:52 PM PDT 24 |
Finished | Jul 13 05:11:58 PM PDT 24 |
Peak memory | 219472 kb |
Host | smart-e551ac4a-181f-4426-97c7-7911e091f3a6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877426911 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3877426911 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_224.2654416425 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 119922980146 ps |
CPU time | 1944.28 seconds |
Started | Jul 13 05:11:35 PM PDT 24 |
Finished | Jul 13 05:44:00 PM PDT 24 |
Peak memory | 395432 kb |
Host | smart-796847a1-cfa1-4e36-992f-a578b792ffab |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2654416425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2654416425 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3827785728 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 127456089400 ps |
CPU time | 2119.58 seconds |
Started | Jul 13 05:11:36 PM PDT 24 |
Finished | Jul 13 05:46:56 PM PDT 24 |
Peak memory | 381800 kb |
Host | smart-f6fc0315-da18-43e8-a21b-e38bec6665d5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3827785728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3827785728 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_384.3321001113 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 272987431847 ps |
CPU time | 1698.55 seconds |
Started | Jul 13 05:11:36 PM PDT 24 |
Finished | Jul 13 05:39:56 PM PDT 24 |
Peak memory | 333580 kb |
Host | smart-85049378-4228-4576-9c03-cd58d4ae4755 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3321001113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3321001113 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_512.2132325727 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 207122727024 ps |
CPU time | 1218.15 seconds |
Started | Jul 13 05:11:35 PM PDT 24 |
Finished | Jul 13 05:31:53 PM PDT 24 |
Peak memory | 300996 kb |
Host | smart-9d3de03c-7dfe-4dbf-90fd-96a684817e40 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2132325727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.2132325727 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_shake_128.1046178477 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 74544279828 ps |
CPU time | 4956.43 seconds |
Started | Jul 13 05:11:46 PM PDT 24 |
Finished | Jul 13 06:34:24 PM PDT 24 |
Peak memory | 649900 kb |
Host | smart-c83c5749-7573-4fb1-8d02-83286321c0f2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1046178477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1046178477 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/16.kmac_test_vectors_shake_256.2681819459 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 110521364794 ps |
CPU time | 4500.31 seconds |
Started | Jul 13 05:11:46 PM PDT 24 |
Finished | Jul 13 06:26:47 PM PDT 24 |
Peak memory | 587260 kb |
Host | smart-40cb5cb2-3537-4aa8-98bc-3cc357a7698b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2681819459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.2681819459 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/16.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/17.kmac_alert_test.884070802 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 22279989 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:12:30 PM PDT 24 |
Finished | Jul 13 05:12:31 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-0f6119d3-ed57-4e3e-9814-7de254179bb2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884070802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.884070802 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_alert_test/latest |
Test location | /workspace/coverage/default/17.kmac_app.866371267 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 17969242230 ps |
CPU time | 279.42 seconds |
Started | Jul 13 05:12:17 PM PDT 24 |
Finished | Jul 13 05:16:57 PM PDT 24 |
Peak memory | 245448 kb |
Host | smart-75f74324-71ca-4735-9334-f6a6b12b1fb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866371267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.866371267 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_app/latest |
Test location | /workspace/coverage/default/17.kmac_burst_write.2483004256 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 12609416414 ps |
CPU time | 124.72 seconds |
Started | Jul 13 05:12:09 PM PDT 24 |
Finished | Jul 13 05:14:14 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-c16cf803-5c2a-45ea-9fd5-4267d82c4478 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483004256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2483004256 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_burst_write/latest |
Test location | /workspace/coverage/default/17.kmac_edn_timeout_error.3176734270 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 613102035 ps |
CPU time | 13.37 seconds |
Started | Jul 13 05:12:25 PM PDT 24 |
Finished | Jul 13 05:12:39 PM PDT 24 |
Peak memory | 219320 kb |
Host | smart-ac730289-d2cf-4a49-b367-46f52c47523f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3176734270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3176734270 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/17.kmac_entropy_mode_error.2335104289 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 49651103 ps |
CPU time | 1.06 seconds |
Started | Jul 13 05:12:31 PM PDT 24 |
Finished | Jul 13 05:12:32 PM PDT 24 |
Peak memory | 218044 kb |
Host | smart-1e133e00-e450-4d38-be3e-8be2f3cf954f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2335104289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2335104289 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/17.kmac_entropy_refresh.4102302519 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 4305169714 ps |
CPU time | 57 seconds |
Started | Jul 13 05:12:26 PM PDT 24 |
Finished | Jul 13 05:13:23 PM PDT 24 |
Peak memory | 228884 kb |
Host | smart-f27ad034-8868-43bf-8fe0-a77df1a6d683 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102302519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4102302519 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/17.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/17.kmac_error.262153031 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 5389103919 ps |
CPU time | 229.43 seconds |
Started | Jul 13 05:12:25 PM PDT 24 |
Finished | Jul 13 05:16:15 PM PDT 24 |
Peak memory | 251344 kb |
Host | smart-7a2e3c9c-8f6d-4dff-a50b-7007815c308c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262153031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.262153031 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_error/latest |
Test location | /workspace/coverage/default/17.kmac_key_error.1880161141 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1716572392 ps |
CPU time | 3.62 seconds |
Started | Jul 13 05:12:24 PM PDT 24 |
Finished | Jul 13 05:12:28 PM PDT 24 |
Peak memory | 222540 kb |
Host | smart-77c6c1c1-9000-4eb5-8445-3d1e50f3e53b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880161141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1880161141 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_key_error/latest |
Test location | /workspace/coverage/default/17.kmac_lc_escalation.1525071351 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 149235494 ps |
CPU time | 1.26 seconds |
Started | Jul 13 05:12:31 PM PDT 24 |
Finished | Jul 13 05:12:33 PM PDT 24 |
Peak memory | 226632 kb |
Host | smart-9c452387-fc01-4697-87bd-db54c79f1973 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525071351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1525071351 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/17.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/17.kmac_long_msg_and_output.3508812673 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 106049147975 ps |
CPU time | 3096.43 seconds |
Started | Jul 13 05:12:01 PM PDT 24 |
Finished | Jul 13 06:03:38 PM PDT 24 |
Peak memory | 456436 kb |
Host | smart-b77af0db-db26-4bf8-b176-532401ff61a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508812673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.3508812673 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/17.kmac_sideload.1561182077 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 23529666493 ps |
CPU time | 187.46 seconds |
Started | Jul 13 05:12:09 PM PDT 24 |
Finished | Jul 13 05:15:17 PM PDT 24 |
Peak memory | 238572 kb |
Host | smart-2e98147f-43f1-4df2-87f8-298ca7db3c9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561182077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1561182077 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_sideload/latest |
Test location | /workspace/coverage/default/17.kmac_smoke.1815396759 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 2906790881 ps |
CPU time | 54.79 seconds |
Started | Jul 13 05:12:02 PM PDT 24 |
Finished | Jul 13 05:12:57 PM PDT 24 |
Peak memory | 226640 kb |
Host | smart-3f8b304e-0074-4500-aabf-8160559478e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815396759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1815396759 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_smoke/latest |
Test location | /workspace/coverage/default/17.kmac_stress_all.84875356 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 29016907537 ps |
CPU time | 2718.61 seconds |
Started | Jul 13 05:12:32 PM PDT 24 |
Finished | Jul 13 05:57:51 PM PDT 24 |
Peak memory | 466528 kb |
Host | smart-447e6344-187c-48f6-a883-df69b95dabdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=84875356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.84875356 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_stress_all/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_kmac.3541808164 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 137786028 ps |
CPU time | 6.15 seconds |
Started | Jul 13 05:12:17 PM PDT 24 |
Finished | Jul 13 05:12:23 PM PDT 24 |
Peak memory | 219480 kb |
Host | smart-b591e43a-bb64-43e0-8ab2-e1dc27090ee6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541808164 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.3541808164 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.650842249 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 123749895 ps |
CPU time | 6.12 seconds |
Started | Jul 13 05:12:17 PM PDT 24 |
Finished | Jul 13 05:12:23 PM PDT 24 |
Peak memory | 219420 kb |
Host | smart-61a126f2-2be8-4bbd-a8ba-8d2bf397d7ea |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650842249 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.kmac_test_vectors_kmac_xof.650842249 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_224.4016523829 |
Short name | T1057 |
Test name | |
Test status | |
Simulation time | 21681825516 ps |
CPU time | 2001.04 seconds |
Started | Jul 13 05:12:10 PM PDT 24 |
Finished | Jul 13 05:45:31 PM PDT 24 |
Peak memory | 392392 kb |
Host | smart-bf29d72d-4e2f-4dd2-9d94-889e378c2e7f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4016523829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.4016523829 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3965679380 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 20129314558 ps |
CPU time | 2021.1 seconds |
Started | Jul 13 05:12:11 PM PDT 24 |
Finished | Jul 13 05:45:52 PM PDT 24 |
Peak memory | 386436 kb |
Host | smart-b54dc629-9b54-4273-868e-3279a2b68429 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3965679380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3965679380 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_384.3325526710 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 30577195035 ps |
CPU time | 1510.48 seconds |
Started | Jul 13 05:12:17 PM PDT 24 |
Finished | Jul 13 05:37:29 PM PDT 24 |
Peak memory | 343832 kb |
Host | smart-803d7245-4b25-4206-97aa-f86363c69411 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3325526710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.3325526710 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_512.733369894 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 21443131605 ps |
CPU time | 1170.56 seconds |
Started | Jul 13 05:12:16 PM PDT 24 |
Finished | Jul 13 05:31:47 PM PDT 24 |
Peak memory | 296632 kb |
Host | smart-841d8d16-32ee-4edd-bbbb-2d71ef52d967 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=733369894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.733369894 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_shake_128.3383693064 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 852761784221 ps |
CPU time | 5694.57 seconds |
Started | Jul 13 05:12:19 PM PDT 24 |
Finished | Jul 13 06:47:15 PM PDT 24 |
Peak memory | 671488 kb |
Host | smart-45674046-3890-4824-90db-42113e023840 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3383693064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3383693064 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/17.kmac_test_vectors_shake_256.1932700044 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 153907275545 ps |
CPU time | 4672.1 seconds |
Started | Jul 13 05:12:20 PM PDT 24 |
Finished | Jul 13 06:30:12 PM PDT 24 |
Peak memory | 570124 kb |
Host | smart-4df7277c-7dec-4238-a164-a5ca99573c75 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1932700044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.1932700044 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/17.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/18.kmac_alert_test.1297515354 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 18903650 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:12:58 PM PDT 24 |
Finished | Jul 13 05:13:00 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-dc75357e-2eab-4440-ad96-78fde8094d6b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297515354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1297515354 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_alert_test/latest |
Test location | /workspace/coverage/default/18.kmac_app.3778719448 |
Short name | T1065 |
Test name | |
Test status | |
Simulation time | 3663489735 ps |
CPU time | 56.3 seconds |
Started | Jul 13 05:12:52 PM PDT 24 |
Finished | Jul 13 05:13:48 PM PDT 24 |
Peak memory | 228200 kb |
Host | smart-91f25e69-f82d-4309-9958-6f5132f39979 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778719448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3778719448 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_app/latest |
Test location | /workspace/coverage/default/18.kmac_burst_write.519316173 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 16376891007 ps |
CPU time | 482.08 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 05:20:42 PM PDT 24 |
Peak memory | 233852 kb |
Host | smart-21dead47-cf27-44d1-89a7-ac0c34e48c4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519316173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.519316173 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_burst_write/latest |
Test location | /workspace/coverage/default/18.kmac_edn_timeout_error.1837764075 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 995688956 ps |
CPU time | 19.65 seconds |
Started | Jul 13 05:12:59 PM PDT 24 |
Finished | Jul 13 05:13:19 PM PDT 24 |
Peak memory | 237820 kb |
Host | smart-0b3cb64c-e00d-4bd0-961f-7d97e1b45f76 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1837764075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1837764075 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/18.kmac_entropy_mode_error.570262654 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 25698608 ps |
CPU time | 1.22 seconds |
Started | Jul 13 05:13:02 PM PDT 24 |
Finished | Jul 13 05:13:03 PM PDT 24 |
Peak memory | 218536 kb |
Host | smart-54731ddd-d60f-4a79-ab1c-c713af2f103f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=570262654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.570262654 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/18.kmac_entropy_refresh.4052368218 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1575113078 ps |
CPU time | 18.93 seconds |
Started | Jul 13 05:12:51 PM PDT 24 |
Finished | Jul 13 05:13:10 PM PDT 24 |
Peak memory | 226612 kb |
Host | smart-f2b4f8e7-884d-411a-a91c-f8899745ba62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052368218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4052368218 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/18.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/18.kmac_error.665572664 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 6498735969 ps |
CPU time | 249.42 seconds |
Started | Jul 13 05:12:52 PM PDT 24 |
Finished | Jul 13 05:17:01 PM PDT 24 |
Peak memory | 251340 kb |
Host | smart-3f4214b8-4238-4e43-8768-7e0e5d492721 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665572664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.665572664 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_error/latest |
Test location | /workspace/coverage/default/18.kmac_key_error.1010589732 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 1264298566 ps |
CPU time | 4.88 seconds |
Started | Jul 13 05:12:52 PM PDT 24 |
Finished | Jul 13 05:12:57 PM PDT 24 |
Peak memory | 223132 kb |
Host | smart-a3ae3f27-3145-4db2-af05-a67e373a1abc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010589732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1010589732 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_key_error/latest |
Test location | /workspace/coverage/default/18.kmac_lc_escalation.1252496119 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 57418152 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:12:59 PM PDT 24 |
Finished | Jul 13 05:13:00 PM PDT 24 |
Peak memory | 226552 kb |
Host | smart-90d35af0-31dd-4b9c-af4a-a8a9b819c99c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252496119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1252496119 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/18.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/18.kmac_long_msg_and_output.1719431223 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 427561993302 ps |
CPU time | 3151.15 seconds |
Started | Jul 13 05:12:32 PM PDT 24 |
Finished | Jul 13 06:05:04 PM PDT 24 |
Peak memory | 464876 kb |
Host | smart-4dcb0a78-a29d-4fac-8419-8a77d44ba66d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719431223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.1719431223 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/18.kmac_sideload.2799308596 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1496669063 ps |
CPU time | 43.96 seconds |
Started | Jul 13 05:12:40 PM PDT 24 |
Finished | Jul 13 05:13:24 PM PDT 24 |
Peak memory | 234816 kb |
Host | smart-6be98313-1778-4c86-a2fd-e37ac89c4374 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799308596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2799308596 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_sideload/latest |
Test location | /workspace/coverage/default/18.kmac_smoke.2659957677 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 1500646042 ps |
CPU time | 30.7 seconds |
Started | Jul 13 05:12:31 PM PDT 24 |
Finished | Jul 13 05:13:02 PM PDT 24 |
Peak memory | 222712 kb |
Host | smart-e83c8f3d-f937-469c-970f-0543a9b3cf8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659957677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2659957677 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_smoke/latest |
Test location | /workspace/coverage/default/18.kmac_stress_all.3466868755 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 39548735466 ps |
CPU time | 843.04 seconds |
Started | Jul 13 05:12:59 PM PDT 24 |
Finished | Jul 13 05:27:02 PM PDT 24 |
Peak memory | 317200 kb |
Host | smart-aeb73314-1702-4754-a873-af81d6f2e5d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3466868755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3466868755 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_stress_all/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_kmac.1050529566 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 431011157 ps |
CPU time | 5.86 seconds |
Started | Jul 13 05:12:40 PM PDT 24 |
Finished | Jul 13 05:12:46 PM PDT 24 |
Peak memory | 219448 kb |
Host | smart-043b11ef-5af5-4ac0-9adb-39443cc778cd |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050529566 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.1050529566 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2634853869 |
Short name | T1040 |
Test name | |
Test status | |
Simulation time | 265128760 ps |
CPU time | 6.12 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 05:12:46 PM PDT 24 |
Peak memory | 218508 kb |
Host | smart-81507322-529f-463a-8d5c-1f500f33c545 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634853869 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2634853869 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_224.1408103360 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 22043040057 ps |
CPU time | 2239.12 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 05:49:59 PM PDT 24 |
Peak memory | 403116 kb |
Host | smart-a4e0f7ab-4d98-4b55-b427-c34f8237f473 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1408103360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.1408103360 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_256.892671493 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 159520541434 ps |
CPU time | 1861.94 seconds |
Started | Jul 13 05:12:40 PM PDT 24 |
Finished | Jul 13 05:43:42 PM PDT 24 |
Peak memory | 378620 kb |
Host | smart-688b21cf-cc46-4500-b0f5-86611b4c3579 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=892671493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.892671493 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_384.2860564435 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 15742243865 ps |
CPU time | 1402.32 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 05:36:01 PM PDT 24 |
Peak memory | 341068 kb |
Host | smart-679e0db3-8305-4393-9075-99778f653a3e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2860564435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.2860564435 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_512.3670004498 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 48989579818 ps |
CPU time | 1163.09 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 05:32:03 PM PDT 24 |
Peak memory | 301932 kb |
Host | smart-e89fef8a-2f6b-497c-b56a-6b69b341a083 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3670004498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3670004498 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_shake_128.3613207350 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 782516184828 ps |
CPU time | 5892.91 seconds |
Started | Jul 13 05:12:39 PM PDT 24 |
Finished | Jul 13 06:50:53 PM PDT 24 |
Peak memory | 661404 kb |
Host | smart-61283723-f086-4316-b37e-3ff6041177b6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3613207350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3613207350 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/18.kmac_test_vectors_shake_256.1765577717 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 234531867514 ps |
CPU time | 4217.85 seconds |
Started | Jul 13 05:12:40 PM PDT 24 |
Finished | Jul 13 06:22:59 PM PDT 24 |
Peak memory | 561724 kb |
Host | smart-616fb91d-8681-46e1-bcda-d9852d365056 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1765577717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1765577717 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/18.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/19.kmac_alert_test.3969621924 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 17110528 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:13:27 PM PDT 24 |
Finished | Jul 13 05:13:28 PM PDT 24 |
Peak memory | 218292 kb |
Host | smart-3e14edc4-f760-458f-aa50-944ebf7d6495 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969621924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3969621924 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_alert_test/latest |
Test location | /workspace/coverage/default/19.kmac_app.1220034783 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 18739545494 ps |
CPU time | 273.42 seconds |
Started | Jul 13 05:13:16 PM PDT 24 |
Finished | Jul 13 05:17:50 PM PDT 24 |
Peak memory | 246656 kb |
Host | smart-fb2a6a6e-eab2-408d-bee6-0e90c58bfdf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220034783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1220034783 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_app/latest |
Test location | /workspace/coverage/default/19.kmac_burst_write.1954148763 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 11798835689 ps |
CPU time | 1152.67 seconds |
Started | Jul 13 05:13:06 PM PDT 24 |
Finished | Jul 13 05:32:19 PM PDT 24 |
Peak memory | 236884 kb |
Host | smart-5b1df6c2-b075-4d17-866d-42e8e81405e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954148763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1954148763 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_burst_write/latest |
Test location | /workspace/coverage/default/19.kmac_edn_timeout_error.3152461778 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 16112319 ps |
CPU time | 0.92 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:13:16 PM PDT 24 |
Peak memory | 218164 kb |
Host | smart-e754844f-08e9-49c7-95a3-c7af3b63b6f2 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3152461778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3152461778 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/19.kmac_entropy_mode_error.2002265536 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 975966657 ps |
CPU time | 17.06 seconds |
Started | Jul 13 05:13:16 PM PDT 24 |
Finished | Jul 13 05:13:34 PM PDT 24 |
Peak memory | 235304 kb |
Host | smart-27db21cc-2184-451d-8a0a-8c9b035d17ba |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2002265536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2002265536 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/19.kmac_entropy_refresh.2333112430 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 11405375486 ps |
CPU time | 272.44 seconds |
Started | Jul 13 05:13:16 PM PDT 24 |
Finished | Jul 13 05:17:49 PM PDT 24 |
Peak memory | 247608 kb |
Host | smart-3eb0d3e2-4e13-497e-ae73-136bffb3c758 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333112430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2333112430 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/19.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/19.kmac_error.679136335 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 22328320935 ps |
CPU time | 156.47 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:15:51 PM PDT 24 |
Peak memory | 255624 kb |
Host | smart-e9b87c7d-685d-46e8-bf41-ce6fec335e4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679136335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.679136335 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_error/latest |
Test location | /workspace/coverage/default/19.kmac_key_error.3192796033 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 3498317185 ps |
CPU time | 7.5 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:13:22 PM PDT 24 |
Peak memory | 224804 kb |
Host | smart-9304c4ee-e496-4ffd-970a-c51743ec0ccb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192796033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3192796033 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_key_error/latest |
Test location | /workspace/coverage/default/19.kmac_lc_escalation.2377457057 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 146735487 ps |
CPU time | 1.62 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:13:16 PM PDT 24 |
Peak memory | 226676 kb |
Host | smart-b7247070-a046-4fb4-be92-0fbf20457041 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377457057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2377457057 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/19.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/19.kmac_long_msg_and_output.3531536915 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 554369726439 ps |
CPU time | 3134.19 seconds |
Started | Jul 13 05:12:59 PM PDT 24 |
Finished | Jul 13 06:05:14 PM PDT 24 |
Peak memory | 477128 kb |
Host | smart-793ad5bc-7fb8-4c92-9059-67277457dbea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531536915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.3531536915 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/19.kmac_sideload.1860920781 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 24779752240 ps |
CPU time | 445.88 seconds |
Started | Jul 13 05:13:07 PM PDT 24 |
Finished | Jul 13 05:20:33 PM PDT 24 |
Peak memory | 251700 kb |
Host | smart-7f8c4bfb-c036-4577-9939-fcac0b3b0a76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860920781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1860920781 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_sideload/latest |
Test location | /workspace/coverage/default/19.kmac_smoke.26338622 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 1385257256 ps |
CPU time | 9.12 seconds |
Started | Jul 13 05:12:58 PM PDT 24 |
Finished | Jul 13 05:13:08 PM PDT 24 |
Peak memory | 223160 kb |
Host | smart-0507abaa-033c-418d-889f-47b6836f448d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26338622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.26338622 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_smoke/latest |
Test location | /workspace/coverage/default/19.kmac_stress_all.3555310596 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 5710239376 ps |
CPU time | 176.25 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:16:11 PM PDT 24 |
Peak memory | 247092 kb |
Host | smart-87be2c7a-b4ef-4ccc-aca9-b1ee1d1c446f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3555310596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3555310596 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_stress_all/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_kmac.3958290728 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 226380819 ps |
CPU time | 6.76 seconds |
Started | Jul 13 05:13:14 PM PDT 24 |
Finished | Jul 13 05:13:22 PM PDT 24 |
Peak memory | 218440 kb |
Host | smart-77dcb2b1-4020-4d1b-b7c8-bd09d6fbe8e3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958290728 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.3958290728 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2252809898 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 780317236 ps |
CPU time | 6.06 seconds |
Started | Jul 13 05:13:16 PM PDT 24 |
Finished | Jul 13 05:13:22 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-df010d4b-eece-4c39-ac39-854e2ae4779d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252809898 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2252809898 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_224.3008621744 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 77283052365 ps |
CPU time | 1946.08 seconds |
Started | Jul 13 05:13:09 PM PDT 24 |
Finished | Jul 13 05:45:35 PM PDT 24 |
Peak memory | 386096 kb |
Host | smart-fa0878f6-383a-4a3b-9fbe-b792799aadbd |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3008621744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3008621744 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3514951303 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 79997053055 ps |
CPU time | 2108.58 seconds |
Started | Jul 13 05:13:08 PM PDT 24 |
Finished | Jul 13 05:48:18 PM PDT 24 |
Peak memory | 393932 kb |
Host | smart-3be77ded-35b2-4b1d-a4a6-b5313d25bf33 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3514951303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3514951303 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_384.4270296311 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 15003758663 ps |
CPU time | 1467.14 seconds |
Started | Jul 13 05:13:09 PM PDT 24 |
Finished | Jul 13 05:37:36 PM PDT 24 |
Peak memory | 337188 kb |
Host | smart-9c3ee4ec-1291-4107-a159-3c72cee52256 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4270296311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.4270296311 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_512.486683896 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 68982804700 ps |
CPU time | 1159.92 seconds |
Started | Jul 13 05:13:09 PM PDT 24 |
Finished | Jul 13 05:32:29 PM PDT 24 |
Peak memory | 296984 kb |
Host | smart-d440ab4e-217c-4293-9f1d-9561ceb5a73b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=486683896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.486683896 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_shake_128.3618491108 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 860728735545 ps |
CPU time | 5586.13 seconds |
Started | Jul 13 05:13:07 PM PDT 24 |
Finished | Jul 13 06:46:14 PM PDT 24 |
Peak memory | 639936 kb |
Host | smart-875b6ce2-2b54-4332-a948-710097b4898f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3618491108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3618491108 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/19.kmac_test_vectors_shake_256.3437433727 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 589516767695 ps |
CPU time | 4120.04 seconds |
Started | Jul 13 05:13:06 PM PDT 24 |
Finished | Jul 13 06:21:47 PM PDT 24 |
Peak memory | 576940 kb |
Host | smart-ca19b913-cc68-4bef-9ccb-0ef2dbdb5f48 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3437433727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.3437433727 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/19.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/2.kmac_alert_test.1979774434 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 66665048 ps |
CPU time | 0.94 seconds |
Started | Jul 13 05:05:46 PM PDT 24 |
Finished | Jul 13 05:05:47 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-492fe891-007b-4761-8c48-b8013fdebb39 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979774434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1979774434 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_alert_test/latest |
Test location | /workspace/coverage/default/2.kmac_app.901384281 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 10526284409 ps |
CPU time | 54.39 seconds |
Started | Jul 13 05:05:42 PM PDT 24 |
Finished | Jul 13 05:06:36 PM PDT 24 |
Peak memory | 228392 kb |
Host | smart-e79013fb-6dbb-403f-9876-4c55b22ac421 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901384281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.901384281 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_app/latest |
Test location | /workspace/coverage/default/2.kmac_app_with_partial_data.572194956 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 23561310480 ps |
CPU time | 154.08 seconds |
Started | Jul 13 05:05:44 PM PDT 24 |
Finished | Jul 13 05:08:18 PM PDT 24 |
Peak memory | 236480 kb |
Host | smart-690bfc6b-5ab1-41a9-baa3-0973257da03b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572194956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.572194956 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/2.kmac_burst_write.3172452089 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 2137729948 ps |
CPU time | 51.09 seconds |
Started | Jul 13 05:05:32 PM PDT 24 |
Finished | Jul 13 05:06:24 PM PDT 24 |
Peak memory | 234756 kb |
Host | smart-c8c3ae1e-f2f9-4059-86dc-9e696f0369fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172452089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3172452089 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_burst_write/latest |
Test location | /workspace/coverage/default/2.kmac_edn_timeout_error.3565956058 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 35260798 ps |
CPU time | 1.03 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 05:05:44 PM PDT 24 |
Peak memory | 218200 kb |
Host | smart-bac3b5b7-dfb4-4b21-b073-25c462db3339 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3565956058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3565956058 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/2.kmac_entropy_mode_error.4079888240 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 33675600 ps |
CPU time | 1.11 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 05:05:44 PM PDT 24 |
Peak memory | 218036 kb |
Host | smart-fdfad77e-5a66-44a9-bbf0-6fb15b03f302 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4079888240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4079888240 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/2.kmac_entropy_ready_error.3335153961 |
Short name | T1045 |
Test name | |
Test status | |
Simulation time | 1849949742 ps |
CPU time | 19 seconds |
Started | Jul 13 05:05:45 PM PDT 24 |
Finished | Jul 13 05:06:04 PM PDT 24 |
Peak memory | 226572 kb |
Host | smart-dff23f2a-4f75-4a03-bb35-ef42d39c8fd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335153961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3335153961 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/2.kmac_entropy_refresh.54704509 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 5418757773 ps |
CPU time | 231.15 seconds |
Started | Jul 13 05:05:41 PM PDT 24 |
Finished | Jul 13 05:09:33 PM PDT 24 |
Peak memory | 244432 kb |
Host | smart-b338c578-ecf1-4acc-aa46-3b387f1f3234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54704509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.54704509 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/2.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/2.kmac_error.2494554078 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 1798274902 ps |
CPU time | 100.2 seconds |
Started | Jul 13 05:05:40 PM PDT 24 |
Finished | Jul 13 05:07:21 PM PDT 24 |
Peak memory | 242908 kb |
Host | smart-bf47025e-5b40-4043-8774-36e375ff12c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494554078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2494554078 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_error/latest |
Test location | /workspace/coverage/default/2.kmac_key_error.2859979441 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 1027484631 ps |
CPU time | 7.76 seconds |
Started | Jul 13 05:05:45 PM PDT 24 |
Finished | Jul 13 05:05:53 PM PDT 24 |
Peak memory | 222740 kb |
Host | smart-b587b84a-e1a4-4c97-940d-855bb31f2c96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859979441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2859979441 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_key_error/latest |
Test location | /workspace/coverage/default/2.kmac_lc_escalation.1208664328 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 39519503 ps |
CPU time | 1.31 seconds |
Started | Jul 13 05:05:40 PM PDT 24 |
Finished | Jul 13 05:05:41 PM PDT 24 |
Peak memory | 226380 kb |
Host | smart-c5c78ea9-3426-4626-be40-1dbbb131b2c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208664328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1208664328 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/2.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/2.kmac_long_msg_and_output.334278725 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 113529163307 ps |
CPU time | 2801.67 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:52:13 PM PDT 24 |
Peak memory | 464952 kb |
Host | smart-17901a27-5aaf-4b0a-9349-8eb7432eeae7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334278725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and _output.334278725 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/2.kmac_mubi.2274249646 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 12635414392 ps |
CPU time | 133.54 seconds |
Started | Jul 13 05:05:41 PM PDT 24 |
Finished | Jul 13 05:07:54 PM PDT 24 |
Peak memory | 236976 kb |
Host | smart-eac3660b-0408-4201-bd21-dda94e0acd16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274249646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2274249646 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_mubi/latest |
Test location | /workspace/coverage/default/2.kmac_sec_cm.3112028816 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 22973589571 ps |
CPU time | 47.53 seconds |
Started | Jul 13 05:05:44 PM PDT 24 |
Finished | Jul 13 05:06:32 PM PDT 24 |
Peak memory | 254248 kb |
Host | smart-1a3bd23f-17bf-4fe1-8658-0992a8649f86 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112028816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3112028816 +enable_maski ng=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_sec_cm/latest |
Test location | /workspace/coverage/default/2.kmac_sideload.3916109051 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 24989247634 ps |
CPU time | 230.98 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:09:22 PM PDT 24 |
Peak memory | 240508 kb |
Host | smart-262291cd-4cdd-4825-b9c7-d7ce54993c31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916109051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3916109051 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_sideload/latest |
Test location | /workspace/coverage/default/2.kmac_smoke.2250214449 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1168443659 ps |
CPU time | 47.09 seconds |
Started | Jul 13 05:05:29 PM PDT 24 |
Finished | Jul 13 05:06:16 PM PDT 24 |
Peak memory | 218332 kb |
Host | smart-ca2148e0-3ea0-4956-81f7-dc9c0a5b48c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250214449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2250214449 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_smoke/latest |
Test location | /workspace/coverage/default/2.kmac_stress_all.2216963280 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 56109604436 ps |
CPU time | 1460.68 seconds |
Started | Jul 13 05:05:40 PM PDT 24 |
Finished | Jul 13 05:30:01 PM PDT 24 |
Peak memory | 375876 kb |
Host | smart-8a797d1c-1bc2-4b61-aefe-053ba00d4c35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2216963280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2216963280 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_stress_all/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_kmac.2781974413 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 289829207 ps |
CPU time | 6.65 seconds |
Started | Jul 13 05:05:41 PM PDT 24 |
Finished | Jul 13 05:05:48 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-7bd8ead7-4222-422f-8211-def8b1bff7f6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781974413 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.2781974413 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3305164028 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 526605402 ps |
CPU time | 5.66 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 05:05:49 PM PDT 24 |
Peak memory | 219452 kb |
Host | smart-6538bff8-1ec6-40cf-b6aa-19cac5060ecf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305164028 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3305164028 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_224.928261898 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 386046454370 ps |
CPU time | 2450.66 seconds |
Started | Jul 13 05:05:30 PM PDT 24 |
Finished | Jul 13 05:46:21 PM PDT 24 |
Peak memory | 394652 kb |
Host | smart-4d24e268-c8e2-42df-874c-692d84736f40 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=928261898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.928261898 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_256.1451236514 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 70687311267 ps |
CPU time | 2108.25 seconds |
Started | Jul 13 05:05:29 PM PDT 24 |
Finished | Jul 13 05:40:38 PM PDT 24 |
Peak memory | 387032 kb |
Host | smart-eff00ac6-6e4a-4b71-ad43-0159b9c6ed6a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1451236514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1451236514 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2891199059 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 67930168191 ps |
CPU time | 1552.96 seconds |
Started | Jul 13 05:05:31 PM PDT 24 |
Finished | Jul 13 05:31:25 PM PDT 24 |
Peak memory | 341892 kb |
Host | smart-7a84f254-da67-4a78-8c01-df13c9152bd5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2891199059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2891199059 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_512.685245832 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 47887266573 ps |
CPU time | 1130.77 seconds |
Started | Jul 13 05:05:46 PM PDT 24 |
Finished | Jul 13 05:24:37 PM PDT 24 |
Peak memory | 299740 kb |
Host | smart-eab805ff-8635-47ac-8605-25c113d13eb5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=685245832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.685245832 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_shake_128.2516966229 |
Short name | T1061 |
Test name | |
Test status | |
Simulation time | 193349014865 ps |
CPU time | 5378.61 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 06:35:23 PM PDT 24 |
Peak memory | 675916 kb |
Host | smart-4227b12c-6e92-4960-b87e-afc9e5ea3cb0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2516966229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2516966229 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/2.kmac_test_vectors_shake_256.10392728 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 151753967341 ps |
CPU time | 4703.72 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 06:24:07 PM PDT 24 |
Peak memory | 573388 kb |
Host | smart-7db72ef1-d832-4ecc-9a4c-59b602e1f5f7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=10392728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.10392728 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/2.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/20.kmac_alert_test.3982100229 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 55894525 ps |
CPU time | 0.91 seconds |
Started | Jul 13 05:13:47 PM PDT 24 |
Finished | Jul 13 05:13:49 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-f2fdf3ae-b75f-4655-9243-26284e527a90 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982100229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3982100229 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_alert_test/latest |
Test location | /workspace/coverage/default/20.kmac_app.1884493013 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 12558231130 ps |
CPU time | 263.4 seconds |
Started | Jul 13 05:13:40 PM PDT 24 |
Finished | Jul 13 05:18:04 PM PDT 24 |
Peak memory | 244376 kb |
Host | smart-0c118c95-97b6-4068-82ea-713ead8ecd0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884493013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1884493013 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_app/latest |
Test location | /workspace/coverage/default/20.kmac_burst_write.4008274858 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 15365378727 ps |
CPU time | 768.58 seconds |
Started | Jul 13 05:13:26 PM PDT 24 |
Finished | Jul 13 05:26:15 PM PDT 24 |
Peak memory | 234328 kb |
Host | smart-f1c1cc51-cd14-4826-8d51-8628e29d2f65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008274858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4008274858 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_burst_write/latest |
Test location | /workspace/coverage/default/20.kmac_error.554071177 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 851253058 ps |
CPU time | 65.89 seconds |
Started | Jul 13 05:13:41 PM PDT 24 |
Finished | Jul 13 05:14:48 PM PDT 24 |
Peak memory | 242988 kb |
Host | smart-eec2f929-6922-41e2-a9f9-117fd6fabdbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554071177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.554071177 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_error/latest |
Test location | /workspace/coverage/default/20.kmac_key_error.2575324623 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 69524921 ps |
CPU time | 1.66 seconds |
Started | Jul 13 05:13:40 PM PDT 24 |
Finished | Jul 13 05:13:42 PM PDT 24 |
Peak memory | 222508 kb |
Host | smart-8129571b-b88c-4b56-a1aa-8db0ae1e5ea4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575324623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2575324623 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_key_error/latest |
Test location | /workspace/coverage/default/20.kmac_long_msg_and_output.3602017844 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 294008434283 ps |
CPU time | 1968.74 seconds |
Started | Jul 13 05:13:26 PM PDT 24 |
Finished | Jul 13 05:46:15 PM PDT 24 |
Peak memory | 364604 kb |
Host | smart-7fc951dd-6225-40fe-9219-bc495eaf1a24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602017844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.3602017844 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/20.kmac_sideload.3074707284 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 74651563909 ps |
CPU time | 368.23 seconds |
Started | Jul 13 05:13:27 PM PDT 24 |
Finished | Jul 13 05:19:35 PM PDT 24 |
Peak memory | 250264 kb |
Host | smart-9217c0b6-2175-4795-b2b4-2f6ba6814738 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074707284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3074707284 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_sideload/latest |
Test location | /workspace/coverage/default/20.kmac_smoke.865991314 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 1110228485 ps |
CPU time | 16.79 seconds |
Started | Jul 13 05:13:27 PM PDT 24 |
Finished | Jul 13 05:13:44 PM PDT 24 |
Peak memory | 222532 kb |
Host | smart-edcff8d4-013a-4bf2-880d-e86b6ef34199 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865991314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.865991314 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_smoke/latest |
Test location | /workspace/coverage/default/20.kmac_stress_all.3191924898 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 10405665869 ps |
CPU time | 510.98 seconds |
Started | Jul 13 05:13:41 PM PDT 24 |
Finished | Jul 13 05:22:12 PM PDT 24 |
Peak memory | 261916 kb |
Host | smart-1cd25bcf-1a06-4990-bc88-79f9f3e33b1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3191924898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3191924898 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_stress_all/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_kmac.938784481 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 300710891 ps |
CPU time | 6.27 seconds |
Started | Jul 13 05:13:35 PM PDT 24 |
Finished | Jul 13 05:13:42 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-f92f6e32-1926-454a-8495-73c6284abbc6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938784481 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.kmac_test_vectors_kmac.938784481 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.4218618664 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 1211021823 ps |
CPU time | 7.49 seconds |
Started | Jul 13 05:13:32 PM PDT 24 |
Finished | Jul 13 05:13:40 PM PDT 24 |
Peak memory | 218476 kb |
Host | smart-81cbc40a-2493-4660-a890-31e759e68b7e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218618664 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.4218618664 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1387135963 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 186639682517 ps |
CPU time | 2135.99 seconds |
Started | Jul 13 05:13:26 PM PDT 24 |
Finished | Jul 13 05:49:03 PM PDT 24 |
Peak memory | 402500 kb |
Host | smart-6983d9c0-37c7-44df-aa5e-b8043ead99a7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1387135963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1387135963 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2750458298 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 39130923392 ps |
CPU time | 1768.21 seconds |
Started | Jul 13 05:13:26 PM PDT 24 |
Finished | Jul 13 05:42:54 PM PDT 24 |
Peak memory | 380464 kb |
Host | smart-e2685da1-63a9-43ff-966a-5b9f259bf461 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2750458298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2750458298 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_384.759334950 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 255762834196 ps |
CPU time | 1767.54 seconds |
Started | Jul 13 05:13:34 PM PDT 24 |
Finished | Jul 13 05:43:02 PM PDT 24 |
Peak memory | 341348 kb |
Host | smart-1f52115c-10e5-4534-a02d-023c8bf81880 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=759334950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.759334950 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1862575020 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 100999710348 ps |
CPU time | 1358.98 seconds |
Started | Jul 13 05:13:35 PM PDT 24 |
Finished | Jul 13 05:36:14 PM PDT 24 |
Peak memory | 297896 kb |
Host | smart-2dcf58f5-469c-4eec-9e8d-e7739066330b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1862575020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1862575020 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_shake_128.766497500 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 426178144878 ps |
CPU time | 5583.49 seconds |
Started | Jul 13 05:13:32 PM PDT 24 |
Finished | Jul 13 06:46:36 PM PDT 24 |
Peak memory | 665172 kb |
Host | smart-1435db3f-d22e-4a25-a2bd-4edabb59e988 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=766497500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.766497500 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/20.kmac_test_vectors_shake_256.1147947729 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 155210075741 ps |
CPU time | 4998.29 seconds |
Started | Jul 13 05:13:33 PM PDT 24 |
Finished | Jul 13 06:36:52 PM PDT 24 |
Peak memory | 579552 kb |
Host | smart-87c5c984-2744-45a9-b5c8-ca8f61516f0d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1147947729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1147947729 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/20.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/21.kmac_alert_test.3015000465 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 47933734 ps |
CPU time | 0.86 seconds |
Started | Jul 13 05:14:02 PM PDT 24 |
Finished | Jul 13 05:14:03 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-1e15cdec-e090-4e78-8684-e7f367b675a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015000465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3015000465 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_alert_test/latest |
Test location | /workspace/coverage/default/21.kmac_app.2903083105 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 5400476241 ps |
CPU time | 343.18 seconds |
Started | Jul 13 05:13:57 PM PDT 24 |
Finished | Jul 13 05:19:40 PM PDT 24 |
Peak memory | 251896 kb |
Host | smart-a248d5b2-13d4-45bb-abe5-83220947ab8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903083105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2903083105 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_app/latest |
Test location | /workspace/coverage/default/21.kmac_burst_write.4101480539 |
Short name | T1074 |
Test name | |
Test status | |
Simulation time | 2831629606 ps |
CPU time | 266.68 seconds |
Started | Jul 13 05:13:56 PM PDT 24 |
Finished | Jul 13 05:18:23 PM PDT 24 |
Peak memory | 228220 kb |
Host | smart-477fc237-8ce8-4f9a-aecf-d759c3b0bb8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101480539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.4101480539 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_burst_write/latest |
Test location | /workspace/coverage/default/21.kmac_entropy_refresh.54250796 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 8357624102 ps |
CPU time | 237.37 seconds |
Started | Jul 13 05:14:02 PM PDT 24 |
Finished | Jul 13 05:18:00 PM PDT 24 |
Peak memory | 244248 kb |
Host | smart-8494873e-1bb3-40fe-916c-215d7a9039d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54250796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.54250796 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/21.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/21.kmac_error.2194895550 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 8055184056 ps |
CPU time | 306.52 seconds |
Started | Jul 13 05:14:03 PM PDT 24 |
Finished | Jul 13 05:19:10 PM PDT 24 |
Peak memory | 259408 kb |
Host | smart-85ff3772-6672-4c9f-bf26-ae67b43ca259 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194895550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2194895550 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_error/latest |
Test location | /workspace/coverage/default/21.kmac_key_error.823721292 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 16565541143 ps |
CPU time | 10.36 seconds |
Started | Jul 13 05:14:00 PM PDT 24 |
Finished | Jul 13 05:14:10 PM PDT 24 |
Peak memory | 225080 kb |
Host | smart-29f3011e-af2d-4409-8208-f6431b1cb5df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823721292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.823721292 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_key_error/latest |
Test location | /workspace/coverage/default/21.kmac_lc_escalation.848593545 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 47319131 ps |
CPU time | 1.37 seconds |
Started | Jul 13 05:14:00 PM PDT 24 |
Finished | Jul 13 05:14:02 PM PDT 24 |
Peak memory | 226616 kb |
Host | smart-0158e522-8afa-4d43-886b-e29861e8fe89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848593545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.848593545 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/21.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/21.kmac_long_msg_and_output.2366917728 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 9892845338 ps |
CPU time | 319.5 seconds |
Started | Jul 13 05:13:47 PM PDT 24 |
Finished | Jul 13 05:19:07 PM PDT 24 |
Peak memory | 249092 kb |
Host | smart-90a27ec6-cc0a-43bd-88b3-753af67d0129 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366917728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.2366917728 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/21.kmac_sideload.2755483032 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 4906538175 ps |
CPU time | 109.94 seconds |
Started | Jul 13 05:13:55 PM PDT 24 |
Finished | Jul 13 05:15:46 PM PDT 24 |
Peak memory | 230532 kb |
Host | smart-a3fba651-93a1-4adb-a343-939ce0fc8f57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755483032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2755483032 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_sideload/latest |
Test location | /workspace/coverage/default/21.kmac_smoke.622544745 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 11505268689 ps |
CPU time | 36.9 seconds |
Started | Jul 13 05:13:46 PM PDT 24 |
Finished | Jul 13 05:14:24 PM PDT 24 |
Peak memory | 222972 kb |
Host | smart-14726c0b-85d1-4ffc-bdd7-26aa8578d8cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622544745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.622544745 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_smoke/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_kmac.3203956597 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 440416446 ps |
CPU time | 5.76 seconds |
Started | Jul 13 05:13:57 PM PDT 24 |
Finished | Jul 13 05:14:03 PM PDT 24 |
Peak memory | 218404 kb |
Host | smart-090c9e14-1169-4872-b4a2-7697c84af3a2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203956597 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.3203956597 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.4076326838 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1706472897 ps |
CPU time | 6.49 seconds |
Started | Jul 13 05:13:57 PM PDT 24 |
Finished | Jul 13 05:14:04 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-14aff3af-edb5-4439-bd33-79d3f4ff087b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076326838 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.4076326838 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_224.3329585322 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 168459459568 ps |
CPU time | 1919.4 seconds |
Started | Jul 13 05:13:56 PM PDT 24 |
Finished | Jul 13 05:45:56 PM PDT 24 |
Peak memory | 398352 kb |
Host | smart-57e0c6bd-b4c6-41ca-9996-b1fe095bd299 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3329585322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3329585322 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_256.1767386262 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 19904749095 ps |
CPU time | 1885.53 seconds |
Started | Jul 13 05:13:57 PM PDT 24 |
Finished | Jul 13 05:45:23 PM PDT 24 |
Peak memory | 388944 kb |
Host | smart-f3619669-7ee9-4011-80ef-4af7a14c4778 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1767386262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.1767386262 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3117500607 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 15267728478 ps |
CPU time | 1489.87 seconds |
Started | Jul 13 05:13:55 PM PDT 24 |
Finished | Jul 13 05:38:45 PM PDT 24 |
Peak memory | 337288 kb |
Host | smart-e183e968-cf0b-4f3e-b53a-2c63b17c4fb0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3117500607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3117500607 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2469780883 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 50718152069 ps |
CPU time | 1251.84 seconds |
Started | Jul 13 05:13:55 PM PDT 24 |
Finished | Jul 13 05:34:48 PM PDT 24 |
Peak memory | 300500 kb |
Host | smart-f2a24fed-0bc8-44f9-b2bc-fa9a93a19259 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2469780883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2469780883 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_shake_128.2190161029 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 534828427427 ps |
CPU time | 6137.74 seconds |
Started | Jul 13 05:13:57 PM PDT 24 |
Finished | Jul 13 06:56:16 PM PDT 24 |
Peak memory | 667460 kb |
Host | smart-2c4e7047-7814-4f0f-9d42-7a6921e4db3e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2190161029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2190161029 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/21.kmac_test_vectors_shake_256.3368923167 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 54561129714 ps |
CPU time | 4370.75 seconds |
Started | Jul 13 05:13:56 PM PDT 24 |
Finished | Jul 13 06:26:47 PM PDT 24 |
Peak memory | 561312 kb |
Host | smart-1010072c-4b18-4175-aef0-b848cc8fde3d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3368923167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3368923167 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/21.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/22.kmac_alert_test.65277933 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 114299788 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:14:25 PM PDT 24 |
Finished | Jul 13 05:14:26 PM PDT 24 |
Peak memory | 218276 kb |
Host | smart-f107a4af-d75d-41fa-9d67-22933cf91347 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65277933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.65277933 +enable_mas king=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_alert_test/latest |
Test location | /workspace/coverage/default/22.kmac_app.1260625787 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 6418168231 ps |
CPU time | 33.69 seconds |
Started | Jul 13 05:14:16 PM PDT 24 |
Finished | Jul 13 05:14:50 PM PDT 24 |
Peak memory | 226732 kb |
Host | smart-7683390d-96bd-4d94-9ac4-26131d161055 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260625787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1260625787 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_app/latest |
Test location | /workspace/coverage/default/22.kmac_burst_write.3325961521 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 13448334593 ps |
CPU time | 594.36 seconds |
Started | Jul 13 05:14:02 PM PDT 24 |
Finished | Jul 13 05:23:57 PM PDT 24 |
Peak memory | 234608 kb |
Host | smart-9ca70a0c-c761-44ba-8d36-c8b21b67f690 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325961521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3325961521 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_burst_write/latest |
Test location | /workspace/coverage/default/22.kmac_entropy_refresh.460408129 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 35068869704 ps |
CPU time | 151.4 seconds |
Started | Jul 13 05:14:16 PM PDT 24 |
Finished | Jul 13 05:16:48 PM PDT 24 |
Peak memory | 237744 kb |
Host | smart-38a889ec-88e6-4d40-a5b2-e77d8dcc9f81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460408129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.460408129 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/22.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/22.kmac_error.3059561764 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 8298052645 ps |
CPU time | 300.38 seconds |
Started | Jul 13 05:14:17 PM PDT 24 |
Finished | Jul 13 05:19:18 PM PDT 24 |
Peak memory | 253660 kb |
Host | smart-73623c1b-9de7-4e9f-ba37-92b7363de3a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059561764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3059561764 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_error/latest |
Test location | /workspace/coverage/default/22.kmac_key_error.315273634 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 6723429993 ps |
CPU time | 10.73 seconds |
Started | Jul 13 05:14:28 PM PDT 24 |
Finished | Jul 13 05:14:39 PM PDT 24 |
Peak memory | 225200 kb |
Host | smart-fcaec0b1-0b67-4db4-acf1-8d912910ef46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315273634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.315273634 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_key_error/latest |
Test location | /workspace/coverage/default/22.kmac_lc_escalation.146401590 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 747701025 ps |
CPU time | 41.53 seconds |
Started | Jul 13 05:14:26 PM PDT 24 |
Finished | Jul 13 05:15:08 PM PDT 24 |
Peak memory | 236408 kb |
Host | smart-c9833521-fced-4ed5-a664-efac144237bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146401590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.146401590 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/22.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/22.kmac_long_msg_and_output.4066596768 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 82977424321 ps |
CPU time | 1058.33 seconds |
Started | Jul 13 05:14:02 PM PDT 24 |
Finished | Jul 13 05:31:41 PM PDT 24 |
Peak memory | 304984 kb |
Host | smart-2b1c773f-8172-49dd-96b6-8ad4c1c9531f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066596768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.4066596768 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/22.kmac_sideload.2481255277 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 16462049083 ps |
CPU time | 131.85 seconds |
Started | Jul 13 05:14:03 PM PDT 24 |
Finished | Jul 13 05:16:15 PM PDT 24 |
Peak memory | 233792 kb |
Host | smart-50c46b77-5af1-4b1e-afe4-de3505dd8d39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481255277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2481255277 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_sideload/latest |
Test location | /workspace/coverage/default/22.kmac_smoke.3632069824 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 11907530424 ps |
CPU time | 75.18 seconds |
Started | Jul 13 05:14:01 PM PDT 24 |
Finished | Jul 13 05:15:17 PM PDT 24 |
Peak memory | 224172 kb |
Host | smart-03197b55-3711-43aa-bbcd-2c1dfebc5782 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632069824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3632069824 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_smoke/latest |
Test location | /workspace/coverage/default/22.kmac_stress_all.2116278752 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 8853138127 ps |
CPU time | 497.03 seconds |
Started | Jul 13 05:14:26 PM PDT 24 |
Finished | Jul 13 05:22:44 PM PDT 24 |
Peak memory | 284504 kb |
Host | smart-0910ea0b-af2d-4832-b400-9bd7afa76ad2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2116278752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2116278752 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_stress_all/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_kmac.2950495585 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1919909562 ps |
CPU time | 6.43 seconds |
Started | Jul 13 05:14:16 PM PDT 24 |
Finished | Jul 13 05:14:23 PM PDT 24 |
Peak memory | 218416 kb |
Host | smart-e0f8b47e-cad9-47cc-9d03-3fbda22b1364 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950495585 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.2950495585 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.967071677 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 226524769 ps |
CPU time | 6.19 seconds |
Started | Jul 13 05:14:19 PM PDT 24 |
Finished | Jul 13 05:14:26 PM PDT 24 |
Peak memory | 219352 kb |
Host | smart-ae060124-f3fc-4c8d-b919-b2996fb6baed |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967071677 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 22.kmac_test_vectors_kmac_xof.967071677 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_224.3775697374 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 83405113896 ps |
CPU time | 2129.11 seconds |
Started | Jul 13 05:14:10 PM PDT 24 |
Finished | Jul 13 05:49:40 PM PDT 24 |
Peak memory | 395808 kb |
Host | smart-09e7c19c-b900-4c28-985f-89db55d14ec5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3775697374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3775697374 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_256.587866562 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 196581759503 ps |
CPU time | 2211.48 seconds |
Started | Jul 13 05:14:09 PM PDT 24 |
Finished | Jul 13 05:51:01 PM PDT 24 |
Peak memory | 388796 kb |
Host | smart-96ce6d4e-0d5e-495e-b806-02842ec53ca3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=587866562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.587866562 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_384.3416783913 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 142578362286 ps |
CPU time | 1880.46 seconds |
Started | Jul 13 05:14:10 PM PDT 24 |
Finished | Jul 13 05:45:31 PM PDT 24 |
Peak memory | 344260 kb |
Host | smart-e264b727-efe0-4177-a93d-7c59ce054fdf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3416783913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.3416783913 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_512.1599285878 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 100295825602 ps |
CPU time | 1359.33 seconds |
Started | Jul 13 05:14:11 PM PDT 24 |
Finished | Jul 13 05:36:51 PM PDT 24 |
Peak memory | 300728 kb |
Host | smart-987b1e5f-70a4-4369-9af7-d9fb2150378d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1599285878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1599285878 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_shake_128.670955702 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 185014532269 ps |
CPU time | 5560.4 seconds |
Started | Jul 13 05:14:18 PM PDT 24 |
Finished | Jul 13 06:46:59 PM PDT 24 |
Peak memory | 684864 kb |
Host | smart-6da1184a-6a95-4fbb-bd2c-aa5713143429 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=670955702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.670955702 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/22.kmac_test_vectors_shake_256.3874824722 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 630913151714 ps |
CPU time | 4968.24 seconds |
Started | Jul 13 05:14:19 PM PDT 24 |
Finished | Jul 13 06:37:08 PM PDT 24 |
Peak memory | 570940 kb |
Host | smart-54c40e47-c8ed-43e2-92ec-5bf243fce29b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3874824722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3874824722 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/22.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/23.kmac_alert_test.30574055 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 17366715 ps |
CPU time | 0.88 seconds |
Started | Jul 13 05:14:51 PM PDT 24 |
Finished | Jul 13 05:14:52 PM PDT 24 |
Peak memory | 218244 kb |
Host | smart-a18c2764-9885-4159-9092-8fa943f6cb3d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.30574055 +enable_mas king=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_alert_test/latest |
Test location | /workspace/coverage/default/23.kmac_app.1190657681 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 19258519475 ps |
CPU time | 138.89 seconds |
Started | Jul 13 05:14:40 PM PDT 24 |
Finished | Jul 13 05:16:59 PM PDT 24 |
Peak memory | 236260 kb |
Host | smart-0427b8d8-05ba-4a6c-b2f0-731e951d113c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190657681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1190657681 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_app/latest |
Test location | /workspace/coverage/default/23.kmac_burst_write.317430312 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2956231911 ps |
CPU time | 297.68 seconds |
Started | Jul 13 05:14:27 PM PDT 24 |
Finished | Jul 13 05:19:25 PM PDT 24 |
Peak memory | 229104 kb |
Host | smart-7b5991cf-e285-46ae-b18c-ada4ec19cb36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317430312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.317430312 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_burst_write/latest |
Test location | /workspace/coverage/default/23.kmac_entropy_refresh.4013543813 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 4565769058 ps |
CPU time | 208.42 seconds |
Started | Jul 13 05:14:47 PM PDT 24 |
Finished | Jul 13 05:18:16 PM PDT 24 |
Peak memory | 242292 kb |
Host | smart-379577fd-de6a-4b18-b3e1-bc35ceff3084 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013543813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4013543813 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/23.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/23.kmac_error.1240115995 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 20766030422 ps |
CPU time | 120.08 seconds |
Started | Jul 13 05:14:44 PM PDT 24 |
Finished | Jul 13 05:16:44 PM PDT 24 |
Peak memory | 253840 kb |
Host | smart-a87c74c8-ba31-4ee4-a343-78aa48027a64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240115995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1240115995 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_error/latest |
Test location | /workspace/coverage/default/23.kmac_key_error.859987342 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 6147421115 ps |
CPU time | 11.13 seconds |
Started | Jul 13 05:14:40 PM PDT 24 |
Finished | Jul 13 05:14:51 PM PDT 24 |
Peak memory | 225244 kb |
Host | smart-8cb41867-6d9a-496e-8ded-33ccfbd64cff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859987342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.859987342 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_key_error/latest |
Test location | /workspace/coverage/default/23.kmac_long_msg_and_output.1833238186 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 80900504370 ps |
CPU time | 2389.75 seconds |
Started | Jul 13 05:14:26 PM PDT 24 |
Finished | Jul 13 05:54:16 PM PDT 24 |
Peak memory | 412448 kb |
Host | smart-7dc179ae-ba02-447a-8c49-d9c7acda647f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833238186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.1833238186 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/23.kmac_sideload.3533575254 |
Short name | T1056 |
Test name | |
Test status | |
Simulation time | 26631669676 ps |
CPU time | 339.27 seconds |
Started | Jul 13 05:14:26 PM PDT 24 |
Finished | Jul 13 05:20:06 PM PDT 24 |
Peak memory | 244048 kb |
Host | smart-4891da13-5916-4380-b716-2df081d02c19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533575254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3533575254 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_sideload/latest |
Test location | /workspace/coverage/default/23.kmac_smoke.993085079 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 1709672599 ps |
CPU time | 25.17 seconds |
Started | Jul 13 05:14:25 PM PDT 24 |
Finished | Jul 13 05:14:50 PM PDT 24 |
Peak memory | 220000 kb |
Host | smart-0b4be89b-6fa7-4653-ad00-674667b08d13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993085079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.993085079 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_smoke/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_kmac.1984100725 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 114134524 ps |
CPU time | 5.71 seconds |
Started | Jul 13 05:14:41 PM PDT 24 |
Finished | Jul 13 05:14:47 PM PDT 24 |
Peak memory | 218564 kb |
Host | smart-37ad9033-c79a-45b5-b857-70b8af9e002c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984100725 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.1984100725 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.2273690055 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 252849150 ps |
CPU time | 6.21 seconds |
Started | Jul 13 05:14:42 PM PDT 24 |
Finished | Jul 13 05:14:49 PM PDT 24 |
Peak memory | 219516 kb |
Host | smart-eff49f1e-3df2-482c-a2a2-dda9273a192a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273690055 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.2273690055 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_224.1712717911 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 41966358080 ps |
CPU time | 1914.66 seconds |
Started | Jul 13 05:14:33 PM PDT 24 |
Finished | Jul 13 05:46:29 PM PDT 24 |
Peak memory | 387196 kb |
Host | smart-4dc422a4-65a3-4f6c-94fd-e007ca39196d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1712717911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1712717911 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_256.538045912 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 79264777059 ps |
CPU time | 1764.22 seconds |
Started | Jul 13 05:14:31 PM PDT 24 |
Finished | Jul 13 05:43:56 PM PDT 24 |
Peak memory | 379996 kb |
Host | smart-e129ee93-aa57-4213-95f1-ed752f97e2f8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=538045912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.538045912 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_384.3748341170 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 70236288025 ps |
CPU time | 1887.87 seconds |
Started | Jul 13 05:14:33 PM PDT 24 |
Finished | Jul 13 05:46:01 PM PDT 24 |
Peak memory | 336568 kb |
Host | smart-e563a5fc-6c8b-4bde-9590-def9af286244 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3748341170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3748341170 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_512.1312338136 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 44371628658 ps |
CPU time | 1077.53 seconds |
Started | Jul 13 05:14:39 PM PDT 24 |
Finished | Jul 13 05:32:37 PM PDT 24 |
Peak memory | 303172 kb |
Host | smart-87b5b036-9e5d-4612-a19a-f35723ca2fde |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1312338136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1312338136 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_shake_128.3954731833 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 103534973102 ps |
CPU time | 5015.94 seconds |
Started | Jul 13 05:14:41 PM PDT 24 |
Finished | Jul 13 06:38:18 PM PDT 24 |
Peak memory | 663232 kb |
Host | smart-b9c53897-8a4e-4fdc-ac79-97ab20b109e5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3954731833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3954731833 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/23.kmac_test_vectors_shake_256.4074005238 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 463324583232 ps |
CPU time | 5115.54 seconds |
Started | Jul 13 05:14:44 PM PDT 24 |
Finished | Jul 13 06:40:00 PM PDT 24 |
Peak memory | 562416 kb |
Host | smart-09f09f32-56ec-43fd-b67b-da8d1e2706f0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4074005238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.4074005238 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/23.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/24.kmac_alert_test.2974879329 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 28037263 ps |
CPU time | 0.88 seconds |
Started | Jul 13 05:15:08 PM PDT 24 |
Finished | Jul 13 05:15:10 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-ae4e0001-e394-481c-b5cd-93a8146872df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974879329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2974879329 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_alert_test/latest |
Test location | /workspace/coverage/default/24.kmac_app.2253339058 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 5048006972 ps |
CPU time | 71.9 seconds |
Started | Jul 13 05:15:05 PM PDT 24 |
Finished | Jul 13 05:16:18 PM PDT 24 |
Peak memory | 229896 kb |
Host | smart-da73500a-40dd-42ff-9b12-79ce4528a5ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253339058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2253339058 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_app/latest |
Test location | /workspace/coverage/default/24.kmac_burst_write.1376210576 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 16804081407 ps |
CPU time | 197.16 seconds |
Started | Jul 13 05:14:51 PM PDT 24 |
Finished | Jul 13 05:18:08 PM PDT 24 |
Peak memory | 227760 kb |
Host | smart-890930f3-9880-40a7-b57e-ffb89ba9fa48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376210576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1376210576 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_burst_write/latest |
Test location | /workspace/coverage/default/24.kmac_entropy_refresh.3864065359 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 47710641314 ps |
CPU time | 103.29 seconds |
Started | Jul 13 05:15:04 PM PDT 24 |
Finished | Jul 13 05:16:48 PM PDT 24 |
Peak memory | 231104 kb |
Host | smart-7130854e-ed20-42dd-a970-d821b47463c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864065359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3864065359 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/24.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/24.kmac_error.81875782 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 3827071852 ps |
CPU time | 33.43 seconds |
Started | Jul 13 05:15:05 PM PDT 24 |
Finished | Jul 13 05:15:39 PM PDT 24 |
Peak memory | 236256 kb |
Host | smart-1b763ba8-eaa6-4049-9354-38b625bc5941 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81875782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.81875782 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_error/latest |
Test location | /workspace/coverage/default/24.kmac_key_error.1744049308 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 17870575747 ps |
CPU time | 8.79 seconds |
Started | Jul 13 05:15:05 PM PDT 24 |
Finished | Jul 13 05:15:14 PM PDT 24 |
Peak memory | 225260 kb |
Host | smart-aa5bb645-29ea-429b-9cf6-f83031a2b3de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744049308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1744049308 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_key_error/latest |
Test location | /workspace/coverage/default/24.kmac_lc_escalation.640907613 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 54864116 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:15:10 PM PDT 24 |
Finished | Jul 13 05:15:12 PM PDT 24 |
Peak memory | 226600 kb |
Host | smart-804b906b-525d-4009-9015-3b3c57ab263f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640907613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.640907613 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/24.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/24.kmac_long_msg_and_output.2339129963 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 117588778618 ps |
CPU time | 1707.6 seconds |
Started | Jul 13 05:14:47 PM PDT 24 |
Finished | Jul 13 05:43:15 PM PDT 24 |
Peak memory | 350776 kb |
Host | smart-21b8f605-f62c-4c76-b61d-ddb2ede82ccf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339129963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.2339129963 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/24.kmac_sideload.1651049301 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 293324299688 ps |
CPU time | 504.58 seconds |
Started | Jul 13 05:14:46 PM PDT 24 |
Finished | Jul 13 05:23:11 PM PDT 24 |
Peak memory | 256424 kb |
Host | smart-a16476d4-3a98-4a1d-a0d7-0f01b52ae987 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651049301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1651049301 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_sideload/latest |
Test location | /workspace/coverage/default/24.kmac_smoke.2557009327 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 262467185 ps |
CPU time | 6.92 seconds |
Started | Jul 13 05:14:51 PM PDT 24 |
Finished | Jul 13 05:14:58 PM PDT 24 |
Peak memory | 218440 kb |
Host | smart-44268778-0026-494f-8b68-a10cfb2aa853 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557009327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2557009327 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_smoke/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_kmac.3758079740 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1077659338 ps |
CPU time | 6.61 seconds |
Started | Jul 13 05:15:06 PM PDT 24 |
Finished | Jul 13 05:15:13 PM PDT 24 |
Peak memory | 218460 kb |
Host | smart-4cafd99b-6828-46f4-aa40-32bb82f1a6b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758079740 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.3758079740 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1256679738 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 784450912 ps |
CPU time | 5.74 seconds |
Started | Jul 13 05:15:05 PM PDT 24 |
Finished | Jul 13 05:15:11 PM PDT 24 |
Peak memory | 219352 kb |
Host | smart-ff7ad4af-3c7c-48a5-8890-1cea3d54822b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256679738 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1256679738 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_224.104767738 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 66648948580 ps |
CPU time | 2140.74 seconds |
Started | Jul 13 05:14:58 PM PDT 24 |
Finished | Jul 13 05:50:39 PM PDT 24 |
Peak memory | 394640 kb |
Host | smart-d36bdf34-c150-4245-b5f3-81fab148def6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=104767738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.104767738 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2563872585 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 123050581773 ps |
CPU time | 1948.69 seconds |
Started | Jul 13 05:14:59 PM PDT 24 |
Finished | Jul 13 05:47:28 PM PDT 24 |
Peak memory | 380324 kb |
Host | smart-e61d632a-0fa9-43d2-afa9-a269a1e60cc2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2563872585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2563872585 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1946127128 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 121842466170 ps |
CPU time | 1731.85 seconds |
Started | Jul 13 05:14:59 PM PDT 24 |
Finished | Jul 13 05:43:52 PM PDT 24 |
Peak memory | 337340 kb |
Host | smart-eee0aa23-234c-4161-b440-17ccdf70503d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1946127128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1946127128 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3798488090 |
Short name | T1054 |
Test name | |
Test status | |
Simulation time | 35897014197 ps |
CPU time | 1206.5 seconds |
Started | Jul 13 05:14:59 PM PDT 24 |
Finished | Jul 13 05:35:06 PM PDT 24 |
Peak memory | 301088 kb |
Host | smart-d4eb47e8-5910-4c81-9360-ff439547318d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3798488090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3798488090 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_shake_128.1646175367 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 246752759571 ps |
CPU time | 4902.52 seconds |
Started | Jul 13 05:15:01 PM PDT 24 |
Finished | Jul 13 06:36:44 PM PDT 24 |
Peak memory | 642336 kb |
Host | smart-240c4118-8182-4209-8adf-4810b026a8ae |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1646175367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.1646175367 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/24.kmac_test_vectors_shake_256.1469926025 |
Short name | T1068 |
Test name | |
Test status | |
Simulation time | 2162984953674 ps |
CPU time | 5365.21 seconds |
Started | Jul 13 05:14:58 PM PDT 24 |
Finished | Jul 13 06:44:24 PM PDT 24 |
Peak memory | 574948 kb |
Host | smart-3678f9b6-647d-484d-8b7d-bbdd489600e9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1469926025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1469926025 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/24.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/25.kmac_alert_test.3371660999 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 12833550 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:15:31 PM PDT 24 |
Finished | Jul 13 05:15:32 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-669ce660-6588-42a3-9b94-0f15eba665a9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371660999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3371660999 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_alert_test/latest |
Test location | /workspace/coverage/default/25.kmac_app.3251112429 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 9172774640 ps |
CPU time | 127.23 seconds |
Started | Jul 13 05:15:22 PM PDT 24 |
Finished | Jul 13 05:17:29 PM PDT 24 |
Peak memory | 236340 kb |
Host | smart-9647379d-7702-455e-a80c-fec05fac1153 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251112429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3251112429 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_app/latest |
Test location | /workspace/coverage/default/25.kmac_burst_write.1677062179 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 65037654965 ps |
CPU time | 1123.81 seconds |
Started | Jul 13 05:15:14 PM PDT 24 |
Finished | Jul 13 05:33:58 PM PDT 24 |
Peak memory | 239096 kb |
Host | smart-0e1ba3d5-5099-47fc-85ea-a65d5466c042 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677062179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1677062179 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_burst_write/latest |
Test location | /workspace/coverage/default/25.kmac_error.1705709695 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 5933656005 ps |
CPU time | 494.33 seconds |
Started | Jul 13 05:15:22 PM PDT 24 |
Finished | Jul 13 05:23:37 PM PDT 24 |
Peak memory | 267576 kb |
Host | smart-5ddb2b68-9db2-46b1-8da7-5c9d3e58fb00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705709695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1705709695 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_error/latest |
Test location | /workspace/coverage/default/25.kmac_key_error.1816369146 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 4439091065 ps |
CPU time | 9.15 seconds |
Started | Jul 13 05:15:22 PM PDT 24 |
Finished | Jul 13 05:15:31 PM PDT 24 |
Peak memory | 225192 kb |
Host | smart-8fd5c06a-44e8-44a9-8ddb-87a2003dd9a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816369146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1816369146 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_key_error/latest |
Test location | /workspace/coverage/default/25.kmac_lc_escalation.163754552 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 53532674 ps |
CPU time | 1.48 seconds |
Started | Jul 13 05:15:31 PM PDT 24 |
Finished | Jul 13 05:15:33 PM PDT 24 |
Peak memory | 226608 kb |
Host | smart-eb166e4a-f5b3-4b24-a75c-d178f148e4dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163754552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.163754552 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/25.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/25.kmac_long_msg_and_output.352878877 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 73254203321 ps |
CPU time | 1074.55 seconds |
Started | Jul 13 05:15:06 PM PDT 24 |
Finished | Jul 13 05:33:01 PM PDT 24 |
Peak memory | 305944 kb |
Host | smart-7af6b769-040d-4215-93f8-d28eb3c9bc2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352878877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an d_output.352878877 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/25.kmac_sideload.814413611 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1702194581 ps |
CPU time | 22.8 seconds |
Started | Jul 13 05:15:07 PM PDT 24 |
Finished | Jul 13 05:15:30 PM PDT 24 |
Peak memory | 226584 kb |
Host | smart-a45972e7-95b5-4fef-bf6a-115b89f37be0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814413611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.814413611 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_sideload/latest |
Test location | /workspace/coverage/default/25.kmac_smoke.1140017741 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 4268188681 ps |
CPU time | 37.54 seconds |
Started | Jul 13 05:15:05 PM PDT 24 |
Finished | Jul 13 05:15:43 PM PDT 24 |
Peak memory | 222628 kb |
Host | smart-c668d926-5935-4dd1-9648-d0f2b94c42b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140017741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1140017741 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_smoke/latest |
Test location | /workspace/coverage/default/25.kmac_stress_all.3655106685 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 53465758382 ps |
CPU time | 1072.68 seconds |
Started | Jul 13 05:15:31 PM PDT 24 |
Finished | Jul 13 05:33:24 PM PDT 24 |
Peak memory | 339504 kb |
Host | smart-4bac0f6d-e7f7-4c34-98a2-cb5880b8dfe1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3655106685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3655106685 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_stress_all/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_kmac.2698607777 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 1692134137 ps |
CPU time | 7.17 seconds |
Started | Jul 13 05:15:24 PM PDT 24 |
Finished | Jul 13 05:15:32 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-32ac1d12-1039-45bd-a32d-3aef5fd6505f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698607777 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.2698607777 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.999056399 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1024310241 ps |
CPU time | 5.91 seconds |
Started | Jul 13 05:15:22 PM PDT 24 |
Finished | Jul 13 05:15:29 PM PDT 24 |
Peak memory | 218540 kb |
Host | smart-8adb3878-d57e-4d2f-9bcf-b72cc300390b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999056399 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 25.kmac_test_vectors_kmac_xof.999056399 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_224.4012864074 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 271743767316 ps |
CPU time | 2223.61 seconds |
Started | Jul 13 05:15:14 PM PDT 24 |
Finished | Jul 13 05:52:19 PM PDT 24 |
Peak memory | 395772 kb |
Host | smart-8f2b5503-aed5-4a12-988d-ac55adb4406f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4012864074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.4012864074 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_256.3048067014 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 725340892654 ps |
CPU time | 2161.41 seconds |
Started | Jul 13 05:15:15 PM PDT 24 |
Finished | Jul 13 05:51:17 PM PDT 24 |
Peak memory | 385016 kb |
Host | smart-acc2939b-d5be-4dc2-b880-228fbd1a93ac |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3048067014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3048067014 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3656314234 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 51898144698 ps |
CPU time | 1729.3 seconds |
Started | Jul 13 05:15:14 PM PDT 24 |
Finished | Jul 13 05:44:04 PM PDT 24 |
Peak memory | 347820 kb |
Host | smart-2d721f20-70f7-4977-af0f-861d717bd66d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3656314234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3656314234 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_512.476379650 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 40350778310 ps |
CPU time | 1258.5 seconds |
Started | Jul 13 05:15:14 PM PDT 24 |
Finished | Jul 13 05:36:13 PM PDT 24 |
Peak memory | 299308 kb |
Host | smart-adee6d8f-1922-4186-84dd-b3fed376f330 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=476379650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.476379650 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_shake_128.2649026966 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 181731119441 ps |
CPU time | 5584.59 seconds |
Started | Jul 13 05:15:14 PM PDT 24 |
Finished | Jul 13 06:48:19 PM PDT 24 |
Peak memory | 669400 kb |
Host | smart-1a1c87d3-d45e-4f67-81ec-1a60a206cf30 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2649026966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2649026966 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/25.kmac_test_vectors_shake_256.445632237 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 218330585175 ps |
CPU time | 5009.75 seconds |
Started | Jul 13 05:15:21 PM PDT 24 |
Finished | Jul 13 06:38:52 PM PDT 24 |
Peak memory | 559428 kb |
Host | smart-49016ded-4fc2-4f8b-b364-2ca5f146dd9f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=445632237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.445632237 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/25.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/26.kmac_alert_test.2986464131 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 16426356 ps |
CPU time | 0.85 seconds |
Started | Jul 13 05:15:56 PM PDT 24 |
Finished | Jul 13 05:15:57 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-a1f8ebdf-f43a-4d8a-9107-479204a96119 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986464131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2986464131 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_alert_test/latest |
Test location | /workspace/coverage/default/26.kmac_app.1740569167 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 32209691200 ps |
CPU time | 173.47 seconds |
Started | Jul 13 05:15:47 PM PDT 24 |
Finished | Jul 13 05:18:41 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-e5a8f8fd-7e2a-410f-be64-4874babd0708 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740569167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1740569167 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_app/latest |
Test location | /workspace/coverage/default/26.kmac_burst_write.3746616903 |
Short name | T1069 |
Test name | |
Test status | |
Simulation time | 5135511880 ps |
CPU time | 497.77 seconds |
Started | Jul 13 05:15:30 PM PDT 24 |
Finished | Jul 13 05:23:48 PM PDT 24 |
Peak memory | 231828 kb |
Host | smart-a353fddf-5be9-4943-b664-9d8a1c1dffcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746616903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3746616903 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_burst_write/latest |
Test location | /workspace/coverage/default/26.kmac_entropy_refresh.514572908 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 6082555159 ps |
CPU time | 48.48 seconds |
Started | Jul 13 05:15:48 PM PDT 24 |
Finished | Jul 13 05:16:37 PM PDT 24 |
Peak memory | 228580 kb |
Host | smart-c9d93796-f6d7-4e9a-b06d-791a45dee319 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514572908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.514572908 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/26.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/26.kmac_error.2166846496 |
Short name | T1051 |
Test name | |
Test status | |
Simulation time | 27545463163 ps |
CPU time | 451.09 seconds |
Started | Jul 13 05:15:58 PM PDT 24 |
Finished | Jul 13 05:23:29 PM PDT 24 |
Peak memory | 267520 kb |
Host | smart-1b8afceb-be1a-4fa2-91d6-7055f60b2808 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166846496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2166846496 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_error/latest |
Test location | /workspace/coverage/default/26.kmac_key_error.143453480 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 4287775985 ps |
CPU time | 8.93 seconds |
Started | Jul 13 05:15:58 PM PDT 24 |
Finished | Jul 13 05:16:07 PM PDT 24 |
Peak memory | 224912 kb |
Host | smart-f21b2321-c03b-4ae0-8c46-ed3a37f8192c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143453480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.143453480 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_key_error/latest |
Test location | /workspace/coverage/default/26.kmac_lc_escalation.3523411071 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 85089286 ps |
CPU time | 1.42 seconds |
Started | Jul 13 05:15:57 PM PDT 24 |
Finished | Jul 13 05:15:58 PM PDT 24 |
Peak memory | 226600 kb |
Host | smart-e723f73b-9117-4673-b349-9cfea5d40837 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523411071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3523411071 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/26.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/26.kmac_long_msg_and_output.3072170918 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 565006100335 ps |
CPU time | 3206.79 seconds |
Started | Jul 13 05:15:32 PM PDT 24 |
Finished | Jul 13 06:09:00 PM PDT 24 |
Peak memory | 480040 kb |
Host | smart-86f8072c-3100-41f4-9c94-3a443b2002b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072170918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.3072170918 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/26.kmac_sideload.905788536 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 12268737956 ps |
CPU time | 404.08 seconds |
Started | Jul 13 05:15:29 PM PDT 24 |
Finished | Jul 13 05:22:13 PM PDT 24 |
Peak memory | 249604 kb |
Host | smart-512e2e36-e77d-4ebc-8a2a-278162891cc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905788536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.905788536 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_sideload/latest |
Test location | /workspace/coverage/default/26.kmac_smoke.2473217883 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 6618391602 ps |
CPU time | 31.85 seconds |
Started | Jul 13 05:15:32 PM PDT 24 |
Finished | Jul 13 05:16:04 PM PDT 24 |
Peak memory | 226616 kb |
Host | smart-0d7d0aa8-a516-4f6f-ac99-6e2e88b1b153 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473217883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2473217883 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_smoke/latest |
Test location | /workspace/coverage/default/26.kmac_stress_all.1095607346 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 1327176238 ps |
CPU time | 16.88 seconds |
Started | Jul 13 05:15:56 PM PDT 24 |
Finished | Jul 13 05:16:13 PM PDT 24 |
Peak memory | 226404 kb |
Host | smart-a18ac321-72f1-4fa4-a2be-3073e496eb44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1095607346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1095607346 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_stress_all/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_kmac.1642410188 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 406227086 ps |
CPU time | 5.89 seconds |
Started | Jul 13 05:15:47 PM PDT 24 |
Finished | Jul 13 05:15:53 PM PDT 24 |
Peak memory | 218532 kb |
Host | smart-98151b91-61c8-4623-be74-d8d108f8e7a5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642410188 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.1642410188 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.938040726 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 289495317 ps |
CPU time | 5.9 seconds |
Started | Jul 13 05:15:46 PM PDT 24 |
Finished | Jul 13 05:15:52 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-d830ef96-4f51-4bd2-8699-b60736dc7427 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938040726 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 26.kmac_test_vectors_kmac_xof.938040726 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_224.4208547425 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 22262593592 ps |
CPU time | 1969.62 seconds |
Started | Jul 13 05:15:30 PM PDT 24 |
Finished | Jul 13 05:48:20 PM PDT 24 |
Peak memory | 394112 kb |
Host | smart-5d766aaf-9f6e-4a9d-a7e7-1ec0308a61ef |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4208547425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.4208547425 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_256.1558188408 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 260971636446 ps |
CPU time | 2209.26 seconds |
Started | Jul 13 05:15:31 PM PDT 24 |
Finished | Jul 13 05:52:21 PM PDT 24 |
Peak memory | 391232 kb |
Host | smart-563a8616-2a21-4673-bab1-b778aac06e4c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1558188408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1558188408 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3937730711 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 22629884739 ps |
CPU time | 1400.62 seconds |
Started | Jul 13 05:15:30 PM PDT 24 |
Finished | Jul 13 05:38:51 PM PDT 24 |
Peak memory | 336500 kb |
Host | smart-c6a7bb41-53b2-4a19-af22-3519fe599fee |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3937730711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3937730711 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_512.1430167351 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 203998533186 ps |
CPU time | 1279.15 seconds |
Started | Jul 13 05:15:40 PM PDT 24 |
Finished | Jul 13 05:36:59 PM PDT 24 |
Peak memory | 300140 kb |
Host | smart-dba3a7e7-4e0b-4d7c-ae9f-19374d794dba |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1430167351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1430167351 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_shake_128.3493776260 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 932763107643 ps |
CPU time | 6253.5 seconds |
Started | Jul 13 05:15:38 PM PDT 24 |
Finished | Jul 13 06:59:53 PM PDT 24 |
Peak memory | 663880 kb |
Host | smart-11b83c45-5b81-4666-93c4-27c5742ff86a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3493776260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3493776260 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/26.kmac_test_vectors_shake_256.78633696 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 53989778337 ps |
CPU time | 4434.27 seconds |
Started | Jul 13 05:15:47 PM PDT 24 |
Finished | Jul 13 06:29:42 PM PDT 24 |
Peak memory | 575908 kb |
Host | smart-68dd226e-2baa-4f93-98e6-57a8f9c4c4bf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=78633696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.78633696 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/26.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/27.kmac_alert_test.3389332405 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 135424379 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:16:20 PM PDT 24 |
Finished | Jul 13 05:16:21 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-6bb2d24f-d97e-4aa1-a85d-1d104249013a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389332405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3389332405 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_alert_test/latest |
Test location | /workspace/coverage/default/27.kmac_app.3704251577 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 22165958153 ps |
CPU time | 157.35 seconds |
Started | Jul 13 05:16:13 PM PDT 24 |
Finished | Jul 13 05:18:51 PM PDT 24 |
Peak memory | 237596 kb |
Host | smart-e240738c-6665-4b00-9aa7-fc057f0a9949 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704251577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3704251577 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_app/latest |
Test location | /workspace/coverage/default/27.kmac_burst_write.3930135470 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 943795997 ps |
CPU time | 101.06 seconds |
Started | Jul 13 05:16:05 PM PDT 24 |
Finished | Jul 13 05:17:46 PM PDT 24 |
Peak memory | 226692 kb |
Host | smart-188bbee8-1137-4e9f-886d-0a2249214a8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930135470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3930135470 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_burst_write/latest |
Test location | /workspace/coverage/default/27.kmac_entropy_refresh.4280341324 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 8181033819 ps |
CPU time | 174.91 seconds |
Started | Jul 13 05:16:13 PM PDT 24 |
Finished | Jul 13 05:19:09 PM PDT 24 |
Peak memory | 238396 kb |
Host | smart-b8e3a26a-2649-451e-9755-cdff552b94c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280341324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4280341324 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/27.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/27.kmac_error.1386661013 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 32176922629 ps |
CPU time | 155.65 seconds |
Started | Jul 13 05:16:11 PM PDT 24 |
Finished | Jul 13 05:18:47 PM PDT 24 |
Peak memory | 259108 kb |
Host | smart-84aa24b1-0953-4f18-8c1c-d5628079e3e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386661013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1386661013 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_error/latest |
Test location | /workspace/coverage/default/27.kmac_key_error.558093008 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 3643655619 ps |
CPU time | 7.87 seconds |
Started | Jul 13 05:16:13 PM PDT 24 |
Finished | Jul 13 05:16:22 PM PDT 24 |
Peak memory | 223648 kb |
Host | smart-4a2abb17-2afc-4b38-a709-8278bd294ddf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558093008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.558093008 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_key_error/latest |
Test location | /workspace/coverage/default/27.kmac_lc_escalation.1967994334 |
Short name | T1047 |
Test name | |
Test status | |
Simulation time | 41737346 ps |
CPU time | 1.29 seconds |
Started | Jul 13 05:16:20 PM PDT 24 |
Finished | Jul 13 05:16:22 PM PDT 24 |
Peak memory | 226536 kb |
Host | smart-24f371f5-2306-44e6-997d-27036fe14080 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967994334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1967994334 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/27.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/27.kmac_long_msg_and_output.1370673646 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 125397676685 ps |
CPU time | 2350.7 seconds |
Started | Jul 13 05:15:57 PM PDT 24 |
Finished | Jul 13 05:55:08 PM PDT 24 |
Peak memory | 409804 kb |
Host | smart-4f0d7657-948d-44ac-980d-b714722e78e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370673646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.1370673646 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/27.kmac_sideload.3486126465 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 19707972478 ps |
CPU time | 365.98 seconds |
Started | Jul 13 05:15:56 PM PDT 24 |
Finished | Jul 13 05:22:02 PM PDT 24 |
Peak memory | 250304 kb |
Host | smart-654d511e-5f32-4dda-a869-e729aaa44c7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486126465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3486126465 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_sideload/latest |
Test location | /workspace/coverage/default/27.kmac_smoke.270819684 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 3253639205 ps |
CPU time | 62.09 seconds |
Started | Jul 13 05:15:56 PM PDT 24 |
Finished | Jul 13 05:16:58 PM PDT 24 |
Peak memory | 222432 kb |
Host | smart-1633da95-744a-46e4-b98c-897217869488 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270819684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.270819684 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_smoke/latest |
Test location | /workspace/coverage/default/27.kmac_stress_all.974002486 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 121559837143 ps |
CPU time | 1235.55 seconds |
Started | Jul 13 05:16:19 PM PDT 24 |
Finished | Jul 13 05:36:55 PM PDT 24 |
Peak memory | 333544 kb |
Host | smart-063d50a1-b798-4fc9-829b-29b4360cc209 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=974002486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.974002486 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_stress_all/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_kmac.1826597429 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 1087621091 ps |
CPU time | 6.49 seconds |
Started | Jul 13 05:16:12 PM PDT 24 |
Finished | Jul 13 05:16:19 PM PDT 24 |
Peak memory | 218548 kb |
Host | smart-879201a5-9427-4291-8918-0e42b6e1d425 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826597429 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.1826597429 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.4051252899 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 231075347 ps |
CPU time | 6.37 seconds |
Started | Jul 13 05:16:12 PM PDT 24 |
Finished | Jul 13 05:16:19 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-57bfed61-91e3-4f33-901f-94341b722979 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051252899 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.4051252899 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_224.500925168 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 21535712638 ps |
CPU time | 2040.52 seconds |
Started | Jul 13 05:16:06 PM PDT 24 |
Finished | Jul 13 05:50:07 PM PDT 24 |
Peak memory | 403900 kb |
Host | smart-7846c7a3-6b6e-40de-b7c2-19916e668ae9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=500925168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.500925168 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_256.2294866030 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 124113850065 ps |
CPU time | 2202.06 seconds |
Started | Jul 13 05:16:05 PM PDT 24 |
Finished | Jul 13 05:52:48 PM PDT 24 |
Peak memory | 387068 kb |
Host | smart-9763691d-9d16-48b7-a2e6-546399efb3f7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2294866030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2294866030 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_384.3623414793 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 122523190750 ps |
CPU time | 1731.4 seconds |
Started | Jul 13 05:16:04 PM PDT 24 |
Finished | Jul 13 05:44:56 PM PDT 24 |
Peak memory | 337112 kb |
Host | smart-584f00c9-015c-4cf2-8342-02b6a33942e4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3623414793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3623414793 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_512.288828035 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 10089061869 ps |
CPU time | 1171.64 seconds |
Started | Jul 13 05:16:05 PM PDT 24 |
Finished | Jul 13 05:35:37 PM PDT 24 |
Peak memory | 294992 kb |
Host | smart-49e46b55-49fc-45a3-808e-fa80cd04ba96 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=288828035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.288828035 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_shake_128.2987597175 |
Short name | T1073 |
Test name | |
Test status | |
Simulation time | 122929892685 ps |
CPU time | 4845.95 seconds |
Started | Jul 13 05:16:05 PM PDT 24 |
Finished | Jul 13 06:36:51 PM PDT 24 |
Peak memory | 651000 kb |
Host | smart-f796ad84-56ef-4f44-a032-9d320d397d0d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2987597175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2987597175 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/27.kmac_test_vectors_shake_256.1704709390 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 822765173679 ps |
CPU time | 5115.32 seconds |
Started | Jul 13 05:16:14 PM PDT 24 |
Finished | Jul 13 06:41:31 PM PDT 24 |
Peak memory | 573224 kb |
Host | smart-09be361c-e696-444c-8ce8-174f1ed65e8e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1704709390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1704709390 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/27.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/28.kmac_alert_test.1725172612 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 16555784 ps |
CPU time | 0.85 seconds |
Started | Jul 13 05:16:35 PM PDT 24 |
Finished | Jul 13 05:16:36 PM PDT 24 |
Peak memory | 218312 kb |
Host | smart-73958a52-688d-4b59-b963-44191e895017 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725172612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1725172612 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_alert_test/latest |
Test location | /workspace/coverage/default/28.kmac_app.376761796 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 37957473324 ps |
CPU time | 256.27 seconds |
Started | Jul 13 05:16:38 PM PDT 24 |
Finished | Jul 13 05:20:54 PM PDT 24 |
Peak memory | 244216 kb |
Host | smart-706f191f-0737-4df3-8746-a5a89e351584 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376761796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.376761796 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_app/latest |
Test location | /workspace/coverage/default/28.kmac_burst_write.3163928314 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 6563877093 ps |
CPU time | 35.61 seconds |
Started | Jul 13 05:16:21 PM PDT 24 |
Finished | Jul 13 05:16:57 PM PDT 24 |
Peak memory | 220140 kb |
Host | smart-5baabd74-86e4-4dbe-9759-94142187cfbe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163928314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3163928314 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_burst_write/latest |
Test location | /workspace/coverage/default/28.kmac_entropy_refresh.320625958 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 7822963329 ps |
CPU time | 242.5 seconds |
Started | Jul 13 05:16:38 PM PDT 24 |
Finished | Jul 13 05:20:41 PM PDT 24 |
Peak memory | 245496 kb |
Host | smart-dc11f430-7a34-49ee-8e08-6b91f81328bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320625958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.320625958 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/28.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/28.kmac_error.3007360204 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 9017637401 ps |
CPU time | 323.4 seconds |
Started | Jul 13 05:16:35 PM PDT 24 |
Finished | Jul 13 05:21:59 PM PDT 24 |
Peak memory | 252240 kb |
Host | smart-9195194f-eafe-4ca5-9dda-3be7038959b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007360204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3007360204 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_error/latest |
Test location | /workspace/coverage/default/28.kmac_key_error.2571855889 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 242829658 ps |
CPU time | 1.32 seconds |
Started | Jul 13 05:16:36 PM PDT 24 |
Finished | Jul 13 05:16:38 PM PDT 24 |
Peak memory | 220972 kb |
Host | smart-5ec4bf15-d036-4f50-9943-ccecfca4c743 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571855889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2571855889 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_key_error/latest |
Test location | /workspace/coverage/default/28.kmac_lc_escalation.3757132696 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 102421467 ps |
CPU time | 1.53 seconds |
Started | Jul 13 05:16:37 PM PDT 24 |
Finished | Jul 13 05:16:39 PM PDT 24 |
Peak memory | 226640 kb |
Host | smart-12bba082-8ca3-42d4-8815-73ee1e806f76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757132696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3757132696 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/28.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/28.kmac_long_msg_and_output.3916465159 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 96515555199 ps |
CPU time | 2492.32 seconds |
Started | Jul 13 05:16:23 PM PDT 24 |
Finished | Jul 13 05:57:56 PM PDT 24 |
Peak memory | 403128 kb |
Host | smart-3c605215-4e46-4893-a75d-839d640a43cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916465159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.3916465159 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/28.kmac_sideload.3508049143 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 132955781817 ps |
CPU time | 453.05 seconds |
Started | Jul 13 05:16:20 PM PDT 24 |
Finished | Jul 13 05:23:54 PM PDT 24 |
Peak memory | 248680 kb |
Host | smart-bb13504c-18ba-4a50-9cdf-116247459e95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508049143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3508049143 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_sideload/latest |
Test location | /workspace/coverage/default/28.kmac_smoke.3348585268 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 24129257763 ps |
CPU time | 41.73 seconds |
Started | Jul 13 05:16:20 PM PDT 24 |
Finished | Jul 13 05:17:02 PM PDT 24 |
Peak memory | 223588 kb |
Host | smart-b3bd7494-a29b-404a-b113-8829f735cb48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348585268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3348585268 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_smoke/latest |
Test location | /workspace/coverage/default/28.kmac_stress_all.304553130 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 44838909167 ps |
CPU time | 1533.84 seconds |
Started | Jul 13 05:16:36 PM PDT 24 |
Finished | Jul 13 05:42:10 PM PDT 24 |
Peak memory | 373620 kb |
Host | smart-281caa05-dfb0-4946-82a5-616750190d4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=304553130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.304553130 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_stress_all/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_kmac.1321860013 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 219168400 ps |
CPU time | 6.17 seconds |
Started | Jul 13 05:16:27 PM PDT 24 |
Finished | Jul 13 05:16:34 PM PDT 24 |
Peak memory | 218472 kb |
Host | smart-4cb141f3-b2db-41da-8407-481b9d20f3a1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321860013 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.1321860013 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3637926486 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 4065070677 ps |
CPU time | 7.44 seconds |
Started | Jul 13 05:16:29 PM PDT 24 |
Finished | Jul 13 05:16:37 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-4860a422-7ddb-4dc5-8827-eb3009d5b936 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637926486 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3637926486 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3131327752 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 104177691573 ps |
CPU time | 2359.4 seconds |
Started | Jul 13 05:16:20 PM PDT 24 |
Finished | Jul 13 05:55:41 PM PDT 24 |
Peak memory | 391200 kb |
Host | smart-15dddc02-4b4a-4ce9-9996-5f44a36bf49b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3131327752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3131327752 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_256.289186817 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 76083715358 ps |
CPU time | 1867.53 seconds |
Started | Jul 13 05:16:21 PM PDT 24 |
Finished | Jul 13 05:47:29 PM PDT 24 |
Peak memory | 374580 kb |
Host | smart-7452c1e4-293e-4632-9c09-01879fa5e51f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=289186817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.289186817 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3291560386 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 47525555628 ps |
CPU time | 1611.47 seconds |
Started | Jul 13 05:16:28 PM PDT 24 |
Finished | Jul 13 05:43:20 PM PDT 24 |
Peak memory | 335668 kb |
Host | smart-90cc1a4c-01e4-4782-b9f8-95a3c40d69e2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3291560386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3291560386 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_512.439404871 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 16109382176 ps |
CPU time | 1179.29 seconds |
Started | Jul 13 05:16:29 PM PDT 24 |
Finished | Jul 13 05:36:09 PM PDT 24 |
Peak memory | 299628 kb |
Host | smart-96646349-09d4-490e-8208-0ffb001b8b5a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=439404871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.439404871 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_shake_128.3387923730 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 372580213015 ps |
CPU time | 5622.21 seconds |
Started | Jul 13 05:16:28 PM PDT 24 |
Finished | Jul 13 06:50:11 PM PDT 24 |
Peak memory | 652084 kb |
Host | smart-9a449a05-eef5-44ea-9d15-f9d1de282ad9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3387923730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3387923730 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/28.kmac_test_vectors_shake_256.2959956798 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 311621804724 ps |
CPU time | 5183.63 seconds |
Started | Jul 13 05:16:29 PM PDT 24 |
Finished | Jul 13 06:42:54 PM PDT 24 |
Peak memory | 573372 kb |
Host | smart-f6f6cd67-8a07-4167-850d-b6e2103fc084 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2959956798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2959956798 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/28.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/29.kmac_alert_test.1640137184 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 26140028 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:17:05 PM PDT 24 |
Finished | Jul 13 05:17:07 PM PDT 24 |
Peak memory | 218248 kb |
Host | smart-31fcb24d-0118-4497-aa3c-d6074eb01b89 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640137184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1640137184 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_alert_test/latest |
Test location | /workspace/coverage/default/29.kmac_app.1391529124 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 9648405668 ps |
CPU time | 316.65 seconds |
Started | Jul 13 05:17:05 PM PDT 24 |
Finished | Jul 13 05:22:22 PM PDT 24 |
Peak memory | 250740 kb |
Host | smart-e7cb6f52-1c7f-43dc-85a2-7fde702ef5f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391529124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1391529124 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_app/latest |
Test location | /workspace/coverage/default/29.kmac_burst_write.484227382 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 34387120620 ps |
CPU time | 1222.05 seconds |
Started | Jul 13 05:16:44 PM PDT 24 |
Finished | Jul 13 05:37:07 PM PDT 24 |
Peak memory | 238968 kb |
Host | smart-02feccb3-1b63-4053-8fc7-a904f0136b8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484227382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.484227382 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_burst_write/latest |
Test location | /workspace/coverage/default/29.kmac_entropy_refresh.1813490756 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 18937552150 ps |
CPU time | 195.29 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:20:22 PM PDT 24 |
Peak memory | 240488 kb |
Host | smart-e56b95b3-63be-4f70-939d-7d6be922b545 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813490756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1813490756 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/29.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/29.kmac_error.1415603404 |
Short name | T1076 |
Test name | |
Test status | |
Simulation time | 6693995249 ps |
CPU time | 89.23 seconds |
Started | Jul 13 05:17:07 PM PDT 24 |
Finished | Jul 13 05:18:37 PM PDT 24 |
Peak memory | 243072 kb |
Host | smart-63ba9d7a-a86d-4587-8ffe-ef340c52f801 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415603404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1415603404 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_error/latest |
Test location | /workspace/coverage/default/29.kmac_key_error.766293212 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 2996686331 ps |
CPU time | 12.49 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:17:19 PM PDT 24 |
Peak memory | 225256 kb |
Host | smart-612b7507-384a-4fa8-921c-c3b211cc4563 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766293212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.766293212 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_key_error/latest |
Test location | /workspace/coverage/default/29.kmac_lc_escalation.766288153 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 131843039 ps |
CPU time | 1.4 seconds |
Started | Jul 13 05:17:07 PM PDT 24 |
Finished | Jul 13 05:17:09 PM PDT 24 |
Peak memory | 226636 kb |
Host | smart-e948af8b-9169-47f8-a1f1-ea778030e2f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766288153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.766288153 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/29.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/29.kmac_long_msg_and_output.185840094 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 191873569143 ps |
CPU time | 1798.93 seconds |
Started | Jul 13 05:16:45 PM PDT 24 |
Finished | Jul 13 05:46:44 PM PDT 24 |
Peak memory | 355244 kb |
Host | smart-881eebd5-7776-45f8-8b19-c829bafd54c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185840094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_an d_output.185840094 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/29.kmac_sideload.1014559138 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 39555117019 ps |
CPU time | 537.88 seconds |
Started | Jul 13 05:16:44 PM PDT 24 |
Finished | Jul 13 05:25:42 PM PDT 24 |
Peak memory | 258896 kb |
Host | smart-f7114f5e-c608-4855-9cd1-3e8a061b1fc3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014559138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1014559138 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_sideload/latest |
Test location | /workspace/coverage/default/29.kmac_smoke.2013281015 |
Short name | T1060 |
Test name | |
Test status | |
Simulation time | 3786213931 ps |
CPU time | 42.06 seconds |
Started | Jul 13 05:16:37 PM PDT 24 |
Finished | Jul 13 05:17:19 PM PDT 24 |
Peak memory | 222616 kb |
Host | smart-422818c6-6f4a-45b9-96ab-404b43cbe823 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013281015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2013281015 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_smoke/latest |
Test location | /workspace/coverage/default/29.kmac_stress_all.655802533 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 1129259789 ps |
CPU time | 24.27 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:17:31 PM PDT 24 |
Peak memory | 225708 kb |
Host | smart-17c28e24-5607-47b5-bac0-d5352632c8d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=655802533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.655802533 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_stress_all/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_kmac.2661063905 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 2771990939 ps |
CPU time | 5.99 seconds |
Started | Jul 13 05:16:52 PM PDT 24 |
Finished | Jul 13 05:16:58 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-5e87df9d-2006-4192-988c-25cde2c5f160 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661063905 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.2661063905 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2030779781 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 314871043 ps |
CPU time | 6.57 seconds |
Started | Jul 13 05:16:53 PM PDT 24 |
Finished | Jul 13 05:17:00 PM PDT 24 |
Peak memory | 219212 kb |
Host | smart-ce77e003-08d4-44db-bd20-2b84f98cdedf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030779781 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2030779781 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3184126577 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 35073803392 ps |
CPU time | 2106.16 seconds |
Started | Jul 13 05:16:44 PM PDT 24 |
Finished | Jul 13 05:51:51 PM PDT 24 |
Peak memory | 404000 kb |
Host | smart-d283a7be-29c8-4ec3-b94a-300a5c1a8201 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3184126577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3184126577 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3947069953 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 125488827471 ps |
CPU time | 2259.07 seconds |
Started | Jul 13 05:16:44 PM PDT 24 |
Finished | Jul 13 05:54:24 PM PDT 24 |
Peak memory | 393000 kb |
Host | smart-74ff8942-0315-4953-bd2c-0a601d947510 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3947069953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3947069953 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1169752650 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 96749576390 ps |
CPU time | 1767.33 seconds |
Started | Jul 13 05:16:44 PM PDT 24 |
Finished | Jul 13 05:46:12 PM PDT 24 |
Peak memory | 333816 kb |
Host | smart-2e9c0c81-c86a-47fc-b6e7-64aff30bce00 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1169752650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1169752650 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1029516387 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 68787204227 ps |
CPU time | 1271.05 seconds |
Started | Jul 13 05:16:53 PM PDT 24 |
Finished | Jul 13 05:38:05 PM PDT 24 |
Peak memory | 303804 kb |
Host | smart-39357075-cfd2-4842-a2f7-bdee46a6a8c1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1029516387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1029516387 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_shake_128.3958022006 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 608899115950 ps |
CPU time | 6312.3 seconds |
Started | Jul 13 05:16:53 PM PDT 24 |
Finished | Jul 13 07:02:07 PM PDT 24 |
Peak memory | 647964 kb |
Host | smart-bf2ed848-4164-42e0-b0ea-4e4d4fe4c756 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3958022006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3958022006 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/29.kmac_test_vectors_shake_256.3627813930 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 144953311769 ps |
CPU time | 4280.84 seconds |
Started | Jul 13 05:16:52 PM PDT 24 |
Finished | Jul 13 06:28:14 PM PDT 24 |
Peak memory | 584996 kb |
Host | smart-00cc4c28-f81e-46db-a07d-e74502e1c900 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3627813930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3627813930 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/29.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/3.kmac_alert_test.2851722486 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 154044734 ps |
CPU time | 0.99 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:06:13 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-9336291a-a1f8-4cc2-8de2-9715472a1f0a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851722486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2851722486 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_alert_test/latest |
Test location | /workspace/coverage/default/3.kmac_app.3945290876 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 2847835254 ps |
CPU time | 75.32 seconds |
Started | Jul 13 05:05:52 PM PDT 24 |
Finished | Jul 13 05:07:08 PM PDT 24 |
Peak memory | 230596 kb |
Host | smart-aecbc706-479d-4215-9dca-6b20b00cc2ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945290876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3945290876 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_app/latest |
Test location | /workspace/coverage/default/3.kmac_app_with_partial_data.2783508948 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 5891413991 ps |
CPU time | 250.58 seconds |
Started | Jul 13 05:05:52 PM PDT 24 |
Finished | Jul 13 05:10:03 PM PDT 24 |
Peak memory | 246508 kb |
Host | smart-0cc73d66-7984-4724-b669-418193b336c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783508948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2783508948 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/3.kmac_burst_write.2305416864 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 18643183495 ps |
CPU time | 674.09 seconds |
Started | Jul 13 05:05:46 PM PDT 24 |
Finished | Jul 13 05:17:00 PM PDT 24 |
Peak memory | 232888 kb |
Host | smart-b2025d0f-7011-4f70-9f55-eb7d85dc554f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305416864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2305416864 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_burst_write/latest |
Test location | /workspace/coverage/default/3.kmac_edn_timeout_error.3633492213 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 20926062 ps |
CPU time | 0.89 seconds |
Started | Jul 13 05:06:00 PM PDT 24 |
Finished | Jul 13 05:06:02 PM PDT 24 |
Peak memory | 218164 kb |
Host | smart-81fabbd0-a52d-4415-9ba4-0b4049e501a2 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3633492213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3633492213 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/3.kmac_entropy_mode_error.4106143640 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 13630335 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:06:15 PM PDT 24 |
Finished | Jul 13 05:06:16 PM PDT 24 |
Peak memory | 218056 kb |
Host | smart-4b3e7969-e62e-4021-bcde-65fab671219f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4106143640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4106143640 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/3.kmac_entropy_ready_error.1408623562 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 19112572456 ps |
CPU time | 48.6 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:07:02 PM PDT 24 |
Peak memory | 226716 kb |
Host | smart-72f1eccb-feaa-4669-b4ea-9d6f307269bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408623562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1408623562 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/3.kmac_entropy_refresh.3339921826 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 19036110018 ps |
CPU time | 210.38 seconds |
Started | Jul 13 05:06:00 PM PDT 24 |
Finished | Jul 13 05:09:31 PM PDT 24 |
Peak memory | 240040 kb |
Host | smart-14a04acc-c59c-4c24-b474-f0fafc6e67e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339921826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3339921826 +enable_masking=1 +s w_key_masked=0 |
Directory | /workspace/3.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/3.kmac_error.834519338 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 1251198803 ps |
CPU time | 45.73 seconds |
Started | Jul 13 05:06:02 PM PDT 24 |
Finished | Jul 13 05:06:48 PM PDT 24 |
Peak memory | 242912 kb |
Host | smart-7cdf6163-1113-467b-8d67-4a656e372689 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834519338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.834519338 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_error/latest |
Test location | /workspace/coverage/default/3.kmac_key_error.3862781002 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 1662886349 ps |
CPU time | 3.83 seconds |
Started | Jul 13 05:06:04 PM PDT 24 |
Finished | Jul 13 05:06:08 PM PDT 24 |
Peak memory | 222788 kb |
Host | smart-ccdc322c-a626-4836-a208-a48524127a37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862781002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3862781002 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_key_error/latest |
Test location | /workspace/coverage/default/3.kmac_lc_escalation.3947535503 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 161380719 ps |
CPU time | 1.41 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:06:14 PM PDT 24 |
Peak memory | 226588 kb |
Host | smart-c54d88b3-a8de-4d50-a878-69ac270fbfc5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947535503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3947535503 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/3.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/3.kmac_long_msg_and_output.206240417 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 6779003047 ps |
CPU time | 683.62 seconds |
Started | Jul 13 05:05:42 PM PDT 24 |
Finished | Jul 13 05:17:06 PM PDT 24 |
Peak memory | 285384 kb |
Host | smart-733ed42f-9c97-454c-8295-fcc5c3da66a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206240417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and _output.206240417 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/3.kmac_mubi.2807519768 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 155606295960 ps |
CPU time | 238.49 seconds |
Started | Jul 13 05:06:00 PM PDT 24 |
Finished | Jul 13 05:09:59 PM PDT 24 |
Peak memory | 242740 kb |
Host | smart-bc652db6-053b-4688-ac49-da9e0d2e4a6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807519768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2807519768 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_mubi/latest |
Test location | /workspace/coverage/default/3.kmac_sec_cm.3594882915 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 33122257650 ps |
CPU time | 121.6 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:08:14 PM PDT 24 |
Peak memory | 300920 kb |
Host | smart-19f516b2-f3e0-4824-9c1a-8cb5c8a7eb1f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594882915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3594882915 +enable_maski ng=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_sec_cm/latest |
Test location | /workspace/coverage/default/3.kmac_sideload.676217233 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 46010962013 ps |
CPU time | 185.89 seconds |
Started | Jul 13 05:05:44 PM PDT 24 |
Finished | Jul 13 05:08:51 PM PDT 24 |
Peak memory | 239076 kb |
Host | smart-b26a094e-01c3-45d5-bb7f-45a08f5dfebe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676217233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.676217233 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_sideload/latest |
Test location | /workspace/coverage/default/3.kmac_smoke.2900116143 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2035828294 ps |
CPU time | 68.91 seconds |
Started | Jul 13 05:05:41 PM PDT 24 |
Finished | Jul 13 05:06:50 PM PDT 24 |
Peak memory | 222464 kb |
Host | smart-9456ebe4-19c2-4bc7-9175-9e389968296b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900116143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2900116143 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_smoke/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_kmac.2155192123 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 375015207 ps |
CPU time | 6.48 seconds |
Started | Jul 13 05:05:52 PM PDT 24 |
Finished | Jul 13 05:05:59 PM PDT 24 |
Peak memory | 218004 kb |
Host | smart-82723e98-1b32-4e7b-b7f2-0bb4320be2c4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155192123 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.2155192123 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2544703511 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 959177268 ps |
CPU time | 6.65 seconds |
Started | Jul 13 05:05:50 PM PDT 24 |
Finished | Jul 13 05:05:57 PM PDT 24 |
Peak memory | 219396 kb |
Host | smart-745eae77-2f45-447b-bfba-47bbf05a213e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544703511 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2544703511 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_224.528118517 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 330860675871 ps |
CPU time | 2537.49 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 05:48:01 PM PDT 24 |
Peak memory | 391800 kb |
Host | smart-154989e6-7888-47c1-943b-42e7bed518cb |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=528118517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.528118517 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1554878215 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 95473266711 ps |
CPU time | 2168.49 seconds |
Started | Jul 13 05:05:43 PM PDT 24 |
Finished | Jul 13 05:41:52 PM PDT 24 |
Peak memory | 387452 kb |
Host | smart-92bc470d-5274-42bb-998d-0b2be6e3925b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1554878215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1554878215 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2783358179 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 244154847665 ps |
CPU time | 1710.33 seconds |
Started | Jul 13 05:05:40 PM PDT 24 |
Finished | Jul 13 05:34:11 PM PDT 24 |
Peak memory | 337292 kb |
Host | smart-55575a0d-585a-4461-94fb-9fec07790e9b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2783358179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2783358179 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_512.926044331 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 178858903966 ps |
CPU time | 1233.9 seconds |
Started | Jul 13 05:05:42 PM PDT 24 |
Finished | Jul 13 05:26:17 PM PDT 24 |
Peak memory | 301360 kb |
Host | smart-aec45e4d-19cd-4232-ad2c-9e7bc9d6d7ac |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=926044331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.926044331 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_shake_128.1993968586 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 513887255754 ps |
CPU time | 5863.15 seconds |
Started | Jul 13 05:05:42 PM PDT 24 |
Finished | Jul 13 06:43:26 PM PDT 24 |
Peak memory | 645600 kb |
Host | smart-32d8257b-65f4-40a0-9713-8b52dabbf47c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1993968586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1993968586 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/3.kmac_test_vectors_shake_256.3721003479 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 52759436234 ps |
CPU time | 4305.54 seconds |
Started | Jul 13 05:05:51 PM PDT 24 |
Finished | Jul 13 06:17:37 PM PDT 24 |
Peak memory | 558872 kb |
Host | smart-1bcd5cb0-5691-4463-8159-4fb1a3e278d6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3721003479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3721003479 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/3.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/30.kmac_alert_test.1106068326 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 14330795 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:17:30 PM PDT 24 |
Finished | Jul 13 05:17:31 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-d62ba7fc-06e6-4397-bb51-6b5088152f56 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106068326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1106068326 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_alert_test/latest |
Test location | /workspace/coverage/default/30.kmac_app.2086955064 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 26157157710 ps |
CPU time | 349.34 seconds |
Started | Jul 13 05:17:25 PM PDT 24 |
Finished | Jul 13 05:23:14 PM PDT 24 |
Peak memory | 252692 kb |
Host | smart-8e8a7231-15bd-4264-816f-c55c84ac363c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086955064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2086955064 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_app/latest |
Test location | /workspace/coverage/default/30.kmac_burst_write.2269928091 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 28224473504 ps |
CPU time | 346.06 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:22:52 PM PDT 24 |
Peak memory | 231068 kb |
Host | smart-368d35d4-698f-4dac-85f3-a6f72a083037 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269928091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2269928091 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_burst_write/latest |
Test location | /workspace/coverage/default/30.kmac_error.1306672139 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 4742234500 ps |
CPU time | 95.61 seconds |
Started | Jul 13 05:17:27 PM PDT 24 |
Finished | Jul 13 05:19:03 PM PDT 24 |
Peak memory | 243108 kb |
Host | smart-478bd83c-8141-430b-b348-b22747940f41 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306672139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1306672139 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_error/latest |
Test location | /workspace/coverage/default/30.kmac_key_error.2051966251 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2064651573 ps |
CPU time | 8.21 seconds |
Started | Jul 13 05:17:27 PM PDT 24 |
Finished | Jul 13 05:17:36 PM PDT 24 |
Peak memory | 224492 kb |
Host | smart-751fb8a8-63cf-41ff-adf1-9c5cba05e1a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051966251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2051966251 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_key_error/latest |
Test location | /workspace/coverage/default/30.kmac_lc_escalation.292442464 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 291319116 ps |
CPU time | 1.33 seconds |
Started | Jul 13 05:17:25 PM PDT 24 |
Finished | Jul 13 05:17:26 PM PDT 24 |
Peak memory | 226552 kb |
Host | smart-8aec7ede-64fb-478a-abff-9bdaddb08b65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292442464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.292442464 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/30.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/30.kmac_long_msg_and_output.771978660 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 78351071722 ps |
CPU time | 1004.03 seconds |
Started | Jul 13 05:17:10 PM PDT 24 |
Finished | Jul 13 05:33:54 PM PDT 24 |
Peak memory | 311368 kb |
Host | smart-32bdeb05-c1e6-419a-9f94-bf6dc1b5b369 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771978660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an d_output.771978660 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/30.kmac_sideload.2664709121 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 24235365781 ps |
CPU time | 296.55 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:22:03 PM PDT 24 |
Peak memory | 245292 kb |
Host | smart-b6461bcf-790f-48bf-aacc-a4b1216baeb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664709121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2664709121 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_sideload/latest |
Test location | /workspace/coverage/default/30.kmac_smoke.2422035294 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 4967383318 ps |
CPU time | 56.42 seconds |
Started | Jul 13 05:17:06 PM PDT 24 |
Finished | Jul 13 05:18:02 PM PDT 24 |
Peak memory | 226548 kb |
Host | smart-0f57cbab-5c0f-446c-804c-de627aec7f9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422035294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2422035294 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_smoke/latest |
Test location | /workspace/coverage/default/30.kmac_stress_all.2455013113 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 69515285984 ps |
CPU time | 861.96 seconds |
Started | Jul 13 05:17:32 PM PDT 24 |
Finished | Jul 13 05:31:55 PM PDT 24 |
Peak memory | 306500 kb |
Host | smart-35381ec4-1663-4999-92b6-f5072f397c15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2455013113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2455013113 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_stress_all/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_kmac.1965182036 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 124350772 ps |
CPU time | 5.97 seconds |
Started | Jul 13 05:17:15 PM PDT 24 |
Finished | Jul 13 05:17:21 PM PDT 24 |
Peak memory | 218708 kb |
Host | smart-04b296e5-0438-4f41-90c5-34c8a1a9c931 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965182036 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.1965182036 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2739748664 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 758147321 ps |
CPU time | 6.05 seconds |
Started | Jul 13 05:17:16 PM PDT 24 |
Finished | Jul 13 05:17:22 PM PDT 24 |
Peak memory | 218452 kb |
Host | smart-9172629e-af0b-4f7a-9395-51840bed2ff8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739748664 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2739748664 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_224.4272606153 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 290694322097 ps |
CPU time | 2120.45 seconds |
Started | Jul 13 05:17:14 PM PDT 24 |
Finished | Jul 13 05:52:35 PM PDT 24 |
Peak memory | 388140 kb |
Host | smart-b5bb5dd4-b6e8-4899-8495-7512d204148c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4272606153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.4272606153 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2157693370 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 163209152287 ps |
CPU time | 2130.32 seconds |
Started | Jul 13 05:17:15 PM PDT 24 |
Finished | Jul 13 05:52:46 PM PDT 24 |
Peak memory | 388836 kb |
Host | smart-c7a2fd11-8753-4e5e-acac-5962fd8729bf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2157693370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2157693370 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_384.1000825817 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 30566872906 ps |
CPU time | 1604.68 seconds |
Started | Jul 13 05:17:13 PM PDT 24 |
Finished | Jul 13 05:43:59 PM PDT 24 |
Peak memory | 342048 kb |
Host | smart-66ea08a1-9a92-4c21-b20c-c2cc2229ff98 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1000825817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1000825817 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_512.1564120055 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 48623013459 ps |
CPU time | 1351.04 seconds |
Started | Jul 13 05:17:15 PM PDT 24 |
Finished | Jul 13 05:39:46 PM PDT 24 |
Peak memory | 298316 kb |
Host | smart-0e80de71-75dd-4c4a-83df-b054e1ab0ffa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1564120055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1564120055 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_shake_128.2364904062 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 514250061890 ps |
CPU time | 5934.05 seconds |
Started | Jul 13 05:17:14 PM PDT 24 |
Finished | Jul 13 06:56:09 PM PDT 24 |
Peak memory | 643428 kb |
Host | smart-80dd5adc-5dce-4058-95b0-8b8d97892ba0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2364904062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2364904062 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/30.kmac_test_vectors_shake_256.2269329315 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 67820457550 ps |
CPU time | 4537.99 seconds |
Started | Jul 13 05:17:15 PM PDT 24 |
Finished | Jul 13 06:32:54 PM PDT 24 |
Peak memory | 574948 kb |
Host | smart-a4bc40de-7cee-4565-84ba-8e67510c8c68 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2269329315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2269329315 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/30.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/31.kmac_alert_test.3641760055 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 249650162 ps |
CPU time | 0.88 seconds |
Started | Jul 13 05:17:56 PM PDT 24 |
Finished | Jul 13 05:17:57 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-f35108fe-22ee-4f68-b3cb-5333bd914acf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641760055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3641760055 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_alert_test/latest |
Test location | /workspace/coverage/default/31.kmac_app.3916499435 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 8817601032 ps |
CPU time | 247.02 seconds |
Started | Jul 13 05:17:49 PM PDT 24 |
Finished | Jul 13 05:21:56 PM PDT 24 |
Peak memory | 243988 kb |
Host | smart-e185bca2-514a-443d-a82c-3440672cbb74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916499435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3916499435 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_app/latest |
Test location | /workspace/coverage/default/31.kmac_burst_write.848034918 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 4578746695 ps |
CPU time | 173.6 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 05:20:31 PM PDT 24 |
Peak memory | 228196 kb |
Host | smart-89034846-8eb5-40ee-a95f-f65b0d989f95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848034918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.848034918 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_burst_write/latest |
Test location | /workspace/coverage/default/31.kmac_entropy_refresh.788290662 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 4185970704 ps |
CPU time | 139.75 seconds |
Started | Jul 13 05:17:47 PM PDT 24 |
Finished | Jul 13 05:20:07 PM PDT 24 |
Peak memory | 236652 kb |
Host | smart-f89a26f5-4281-4b05-aacf-e0e6389329aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788290662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.788290662 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/31.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/31.kmac_error.4033054982 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 25239732674 ps |
CPU time | 156.17 seconds |
Started | Jul 13 05:17:47 PM PDT 24 |
Finished | Jul 13 05:20:23 PM PDT 24 |
Peak memory | 251252 kb |
Host | smart-73c3bbfa-e4c7-4f1d-881e-bd7e9ba90f21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033054982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4033054982 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_error/latest |
Test location | /workspace/coverage/default/31.kmac_key_error.1689235188 |
Short name | T1063 |
Test name | |
Test status | |
Simulation time | 3347815009 ps |
CPU time | 11.58 seconds |
Started | Jul 13 05:17:47 PM PDT 24 |
Finished | Jul 13 05:17:59 PM PDT 24 |
Peak memory | 224868 kb |
Host | smart-af7504c1-72d2-4cb0-b285-960346577c86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689235188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1689235188 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_key_error/latest |
Test location | /workspace/coverage/default/31.kmac_long_msg_and_output.1281074020 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 19221698656 ps |
CPU time | 953.26 seconds |
Started | Jul 13 05:17:32 PM PDT 24 |
Finished | Jul 13 05:33:26 PM PDT 24 |
Peak memory | 309696 kb |
Host | smart-f164508f-61d6-4eaa-8cd5-1e93214b8722 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281074020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.1281074020 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/31.kmac_sideload.2333285744 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 37118870498 ps |
CPU time | 494.66 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 05:25:52 PM PDT 24 |
Peak memory | 257780 kb |
Host | smart-e0735ade-d5e3-43a5-9016-4595af5c737c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333285744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2333285744 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_sideload/latest |
Test location | /workspace/coverage/default/31.kmac_smoke.2886391586 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 117946312 ps |
CPU time | 1.43 seconds |
Started | Jul 13 05:17:30 PM PDT 24 |
Finished | Jul 13 05:17:31 PM PDT 24 |
Peak memory | 221744 kb |
Host | smart-f93917e9-a2f4-4df6-97f1-b275528811e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886391586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2886391586 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_smoke/latest |
Test location | /workspace/coverage/default/31.kmac_stress_all.3532450301 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 40281616013 ps |
CPU time | 138.44 seconds |
Started | Jul 13 05:17:47 PM PDT 24 |
Finished | Jul 13 05:20:05 PM PDT 24 |
Peak memory | 251212 kb |
Host | smart-1373842c-606c-48bc-b4e5-7af573679634 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3532450301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3532450301 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_stress_all/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_kmac.2982186886 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 156211355 ps |
CPU time | 5.61 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 05:17:43 PM PDT 24 |
Peak memory | 218420 kb |
Host | smart-06b8cd2c-f08e-49c1-95ac-ecdcf2856c9f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982186886 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.2982186886 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.116918407 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 303709917 ps |
CPU time | 6.1 seconds |
Started | Jul 13 05:17:47 PM PDT 24 |
Finished | Jul 13 05:17:53 PM PDT 24 |
Peak memory | 218480 kb |
Host | smart-e232fa80-650c-4d10-813a-d919fcc90c30 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116918407 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 31.kmac_test_vectors_kmac_xof.116918407 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_224.1730634650 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 179197991286 ps |
CPU time | 2197.2 seconds |
Started | Jul 13 05:17:38 PM PDT 24 |
Finished | Jul 13 05:54:15 PM PDT 24 |
Peak memory | 396064 kb |
Host | smart-7397d99a-9cfe-4036-9287-ce65bf8ed670 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1730634650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1730634650 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_256.32207851 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 61787076426 ps |
CPU time | 2004.76 seconds |
Started | Jul 13 05:17:38 PM PDT 24 |
Finished | Jul 13 05:51:03 PM PDT 24 |
Peak memory | 385968 kb |
Host | smart-0c625426-8bd2-47d0-aed2-a5207966b8da |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=32207851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.32207851 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_384.684965162 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 74736435085 ps |
CPU time | 1898 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 05:49:16 PM PDT 24 |
Peak memory | 346532 kb |
Host | smart-74ba0a16-671b-4400-b337-240e08a67631 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=684965162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.684965162 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_512.3124319178 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 33094004435 ps |
CPU time | 1243.58 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 05:38:21 PM PDT 24 |
Peak memory | 298292 kb |
Host | smart-0dba0241-5d69-4595-9cc4-f1435128b7ff |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3124319178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.3124319178 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_shake_128.1558697136 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 124965937815 ps |
CPU time | 5107.77 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 06:42:46 PM PDT 24 |
Peak memory | 645704 kb |
Host | smart-3c284240-ce93-40b8-94f5-7e284f5a5138 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1558697136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1558697136 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/31.kmac_test_vectors_shake_256.3721959455 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 154262341983 ps |
CPU time | 4702.62 seconds |
Started | Jul 13 05:17:37 PM PDT 24 |
Finished | Jul 13 06:36:01 PM PDT 24 |
Peak memory | 576600 kb |
Host | smart-f68b242d-cfc9-47eb-b75b-ff30641acb77 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3721959455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3721959455 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/31.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/32.kmac_alert_test.674466466 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 15890636 ps |
CPU time | 0.86 seconds |
Started | Jul 13 05:18:14 PM PDT 24 |
Finished | Jul 13 05:18:15 PM PDT 24 |
Peak memory | 218264 kb |
Host | smart-969faf91-1c2e-417b-aabb-391ddd27e62f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674466466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.674466466 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_alert_test/latest |
Test location | /workspace/coverage/default/32.kmac_app.2837666421 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1476598963 ps |
CPU time | 87.44 seconds |
Started | Jul 13 05:18:16 PM PDT 24 |
Finished | Jul 13 05:19:44 PM PDT 24 |
Peak memory | 232316 kb |
Host | smart-84f8ba7f-02b4-4c68-857b-a50d25fd8268 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837666421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2837666421 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_app/latest |
Test location | /workspace/coverage/default/32.kmac_burst_write.4092638824 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 15278219197 ps |
CPU time | 1399.22 seconds |
Started | Jul 13 05:18:04 PM PDT 24 |
Finished | Jul 13 05:41:24 PM PDT 24 |
Peak memory | 236796 kb |
Host | smart-f76ca103-bd57-4c08-826a-8588c7414a62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092638824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.4092638824 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_burst_write/latest |
Test location | /workspace/coverage/default/32.kmac_entropy_refresh.175562613 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 5363432342 ps |
CPU time | 315.04 seconds |
Started | Jul 13 05:18:14 PM PDT 24 |
Finished | Jul 13 05:23:29 PM PDT 24 |
Peak memory | 252656 kb |
Host | smart-15fc32c9-25b6-4eaf-9ffd-dfbe66e95dc3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175562613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.175562613 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/32.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/32.kmac_error.612588208 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 15173292368 ps |
CPU time | 232.64 seconds |
Started | Jul 13 05:18:14 PM PDT 24 |
Finished | Jul 13 05:22:07 PM PDT 24 |
Peak memory | 253308 kb |
Host | smart-db418f95-9f97-470e-b88d-5e40760a54dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612588208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.612588208 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_error/latest |
Test location | /workspace/coverage/default/32.kmac_key_error.201430918 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 51478853 ps |
CPU time | 1.46 seconds |
Started | Jul 13 05:18:13 PM PDT 24 |
Finished | Jul 13 05:18:15 PM PDT 24 |
Peak memory | 222108 kb |
Host | smart-ca087dde-4474-40b0-95cd-d058ab4a5c07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201430918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.201430918 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_key_error/latest |
Test location | /workspace/coverage/default/32.kmac_lc_escalation.725297999 |
Short name | T1043 |
Test name | |
Test status | |
Simulation time | 39542091 ps |
CPU time | 1.43 seconds |
Started | Jul 13 05:18:14 PM PDT 24 |
Finished | Jul 13 05:18:15 PM PDT 24 |
Peak memory | 226676 kb |
Host | smart-4c9327e0-bb06-4478-9768-c0103c75677e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725297999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.725297999 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/32.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/32.kmac_long_msg_and_output.1291157705 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 12567586192 ps |
CPU time | 320.07 seconds |
Started | Jul 13 05:17:56 PM PDT 24 |
Finished | Jul 13 05:23:16 PM PDT 24 |
Peak memory | 253732 kb |
Host | smart-b352acb8-150c-4b01-b6bf-7a27decde30a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291157705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.1291157705 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/32.kmac_sideload.2379425359 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 14847604206 ps |
CPU time | 119.58 seconds |
Started | Jul 13 05:17:55 PM PDT 24 |
Finished | Jul 13 05:19:55 PM PDT 24 |
Peak memory | 233328 kb |
Host | smart-68098a75-47c0-4a14-9ea0-e1083897a4fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379425359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2379425359 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_sideload/latest |
Test location | /workspace/coverage/default/32.kmac_smoke.415765245 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 17703180558 ps |
CPU time | 96.58 seconds |
Started | Jul 13 05:17:56 PM PDT 24 |
Finished | Jul 13 05:19:32 PM PDT 24 |
Peak memory | 226648 kb |
Host | smart-0d991016-04a3-4063-a0e7-e77ac49feefb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415765245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.415765245 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_smoke/latest |
Test location | /workspace/coverage/default/32.kmac_stress_all.1260687007 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 991143565459 ps |
CPU time | 2055.95 seconds |
Started | Jul 13 05:18:13 PM PDT 24 |
Finished | Jul 13 05:52:30 PM PDT 24 |
Peak memory | 407648 kb |
Host | smart-025d4983-95d7-4694-9fe1-45f258801b38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1260687007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1260687007 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_stress_all/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_kmac.4215162355 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 536325487 ps |
CPU time | 6.33 seconds |
Started | Jul 13 05:18:13 PM PDT 24 |
Finished | Jul 13 05:18:20 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-a8a3fef7-e367-4867-af2b-8097f97d084d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215162355 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.kmac_test_vectors_kmac.4215162355 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.598670307 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 131371759 ps |
CPU time | 6.07 seconds |
Started | Jul 13 05:18:13 PM PDT 24 |
Finished | Jul 13 05:18:20 PM PDT 24 |
Peak memory | 219468 kb |
Host | smart-1101cf9d-37b1-403a-9e0c-f3e3af3562ac |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598670307 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 32.kmac_test_vectors_kmac_xof.598670307 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_224.4286229066 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 410584891070 ps |
CPU time | 1866.14 seconds |
Started | Jul 13 05:18:05 PM PDT 24 |
Finished | Jul 13 05:49:12 PM PDT 24 |
Peak memory | 401528 kb |
Host | smart-febab96e-521c-4001-9d86-842dbed6bfd2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4286229066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.4286229066 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_256.3712089338 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 209068859131 ps |
CPU time | 2093.45 seconds |
Started | Jul 13 05:18:04 PM PDT 24 |
Finished | Jul 13 05:52:58 PM PDT 24 |
Peak memory | 392028 kb |
Host | smart-e54dca70-4c1c-4845-a995-e5c4eab978a9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3712089338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3712089338 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2839209972 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 137379809341 ps |
CPU time | 1686.6 seconds |
Started | Jul 13 05:18:04 PM PDT 24 |
Finished | Jul 13 05:46:11 PM PDT 24 |
Peak memory | 333572 kb |
Host | smart-eea8b50b-3b65-4a34-8646-946fc4c7445d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2839209972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2839209972 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_512.368053674 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 86808812990 ps |
CPU time | 1140.44 seconds |
Started | Jul 13 05:18:04 PM PDT 24 |
Finished | Jul 13 05:37:05 PM PDT 24 |
Peak memory | 305272 kb |
Host | smart-b08756d7-f7dd-4dd0-bc6a-de17c8f55dd6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=368053674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.368053674 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_shake_128.288548623 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 288271189643 ps |
CPU time | 5951.06 seconds |
Started | Jul 13 05:18:05 PM PDT 24 |
Finished | Jul 13 06:57:17 PM PDT 24 |
Peak memory | 670384 kb |
Host | smart-a371c14e-4f81-4c15-a42a-de1d6e4b11f8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=288548623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.288548623 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/32.kmac_test_vectors_shake_256.1578356887 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 218986461803 ps |
CPU time | 4347.63 seconds |
Started | Jul 13 05:18:15 PM PDT 24 |
Finished | Jul 13 06:30:44 PM PDT 24 |
Peak memory | 569364 kb |
Host | smart-b5a09da6-0a20-4f14-8a25-cff5d79b0f02 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1578356887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1578356887 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/32.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/33.kmac_alert_test.632731087 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 64140988 ps |
CPU time | 0.92 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:18:40 PM PDT 24 |
Peak memory | 218244 kb |
Host | smart-db5a9220-d79b-4bc9-b6b8-848cb21c2ea3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632731087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.632731087 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_alert_test/latest |
Test location | /workspace/coverage/default/33.kmac_app.679742261 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 17635384984 ps |
CPU time | 240.65 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:22:40 PM PDT 24 |
Peak memory | 243812 kb |
Host | smart-775abf46-aed3-4e3f-82a3-294cb2f20868 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679742261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.679742261 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_app/latest |
Test location | /workspace/coverage/default/33.kmac_burst_write.81785280 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 29696112409 ps |
CPU time | 1089.16 seconds |
Started | Jul 13 05:18:22 PM PDT 24 |
Finished | Jul 13 05:36:31 PM PDT 24 |
Peak memory | 243016 kb |
Host | smart-54cd0f64-4917-4b01-94ad-aa2091c77b1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81785280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.81785280 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_burst_write/latest |
Test location | /workspace/coverage/default/33.kmac_entropy_refresh.1320224043 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 27374286157 ps |
CPU time | 141.2 seconds |
Started | Jul 13 05:18:41 PM PDT 24 |
Finished | Jul 13 05:21:02 PM PDT 24 |
Peak memory | 237952 kb |
Host | smart-045e2e08-1ef9-4444-87b1-fd81fa74d8cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320224043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1320224043 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/33.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/33.kmac_error.2498303867 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 4174383166 ps |
CPU time | 99.92 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:20:20 PM PDT 24 |
Peak memory | 243032 kb |
Host | smart-12eb53cd-47db-46a8-82f5-be40b8043910 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498303867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2498303867 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_error/latest |
Test location | /workspace/coverage/default/33.kmac_key_error.2992577701 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 4490387607 ps |
CPU time | 8.7 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:18:48 PM PDT 24 |
Peak memory | 225052 kb |
Host | smart-b6f58681-0c3f-4053-bcb2-233f8cc38b83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992577701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2992577701 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_key_error/latest |
Test location | /workspace/coverage/default/33.kmac_lc_escalation.709364081 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 124238970 ps |
CPU time | 6.45 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:18:46 PM PDT 24 |
Peak memory | 226708 kb |
Host | smart-55a65d2d-2def-4998-9096-1c38116a59a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709364081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.709364081 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/33.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/33.kmac_long_msg_and_output.2143071998 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 148928289797 ps |
CPU time | 1981.84 seconds |
Started | Jul 13 05:18:22 PM PDT 24 |
Finished | Jul 13 05:51:25 PM PDT 24 |
Peak memory | 356972 kb |
Host | smart-1eeb7984-0987-4601-afea-464dd709b2e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143071998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.2143071998 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/33.kmac_sideload.2085850897 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 15688749484 ps |
CPU time | 388.95 seconds |
Started | Jul 13 05:18:22 PM PDT 24 |
Finished | Jul 13 05:24:52 PM PDT 24 |
Peak memory | 250608 kb |
Host | smart-ab9caf17-6eb3-4824-b0eb-6aa810ebc1dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085850897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2085850897 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_sideload/latest |
Test location | /workspace/coverage/default/33.kmac_smoke.3140548879 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 2999871749 ps |
CPU time | 72.6 seconds |
Started | Jul 13 05:18:14 PM PDT 24 |
Finished | Jul 13 05:19:27 PM PDT 24 |
Peak memory | 218828 kb |
Host | smart-6cf46d8a-b3be-421a-b0cf-f818c17ba0cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140548879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3140548879 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_smoke/latest |
Test location | /workspace/coverage/default/33.kmac_stress_all.328816987 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 71121867245 ps |
CPU time | 191.37 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:21:51 PM PDT 24 |
Peak memory | 265392 kb |
Host | smart-44f5d432-6cbf-406d-9e86-79248b6ad652 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=328816987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.328816987 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_stress_all/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_kmac.1742596147 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 658237776 ps |
CPU time | 7.79 seconds |
Started | Jul 13 05:18:31 PM PDT 24 |
Finished | Jul 13 05:18:41 PM PDT 24 |
Peak memory | 218404 kb |
Host | smart-cfb3c117-b9d1-462a-9aa9-add9a3bfe929 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742596147 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.1742596147 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3721282541 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 551560421 ps |
CPU time | 6.97 seconds |
Started | Jul 13 05:18:32 PM PDT 24 |
Finished | Jul 13 05:18:40 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-63e07c16-be05-4254-a383-c15637d39329 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721282541 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3721282541 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_224.503760121 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 40806781891 ps |
CPU time | 1931.67 seconds |
Started | Jul 13 05:18:23 PM PDT 24 |
Finished | Jul 13 05:50:35 PM PDT 24 |
Peak memory | 389532 kb |
Host | smart-26ad5d4d-9b28-4418-b4ee-c40a6038ac43 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=503760121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.503760121 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3173936563 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 330301403646 ps |
CPU time | 2446.13 seconds |
Started | Jul 13 05:18:21 PM PDT 24 |
Finished | Jul 13 05:59:08 PM PDT 24 |
Peak memory | 389516 kb |
Host | smart-d02a0e6b-16aa-4a25-ae49-69a67aea62c2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3173936563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3173936563 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_384.1013082562 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 255788474154 ps |
CPU time | 1862.85 seconds |
Started | Jul 13 05:18:32 PM PDT 24 |
Finished | Jul 13 05:49:36 PM PDT 24 |
Peak memory | 341776 kb |
Host | smart-bb4d10bc-775d-4b57-bded-4f721774ac56 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1013082562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.1013082562 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3389325924 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 35492731704 ps |
CPU time | 1257.01 seconds |
Started | Jul 13 05:18:33 PM PDT 24 |
Finished | Jul 13 05:39:30 PM PDT 24 |
Peak memory | 299752 kb |
Host | smart-1c8f27d7-8f2c-48d9-9de8-aac7956456b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3389325924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3389325924 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_shake_128.2304458990 |
Short name | T1053 |
Test name | |
Test status | |
Simulation time | 250842321993 ps |
CPU time | 5054.92 seconds |
Started | Jul 13 05:18:32 PM PDT 24 |
Finished | Jul 13 06:42:48 PM PDT 24 |
Peak memory | 666312 kb |
Host | smart-1e1c6374-b20f-4a9e-9d91-eb68506868d1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2304458990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2304458990 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/33.kmac_test_vectors_shake_256.1042930335 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 53490797498 ps |
CPU time | 4303.25 seconds |
Started | Jul 13 05:18:32 PM PDT 24 |
Finished | Jul 13 06:30:17 PM PDT 24 |
Peak memory | 570152 kb |
Host | smart-63e6c6ba-08fe-4029-a3ae-750bcf7905b8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1042930335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1042930335 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/33.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/34.kmac_alert_test.2996396539 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 23839224 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:19:07 PM PDT 24 |
Finished | Jul 13 05:19:08 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-5fd3c67b-63c8-480d-8a55-bf1245063c32 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996396539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2996396539 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_alert_test/latest |
Test location | /workspace/coverage/default/34.kmac_app.1990502098 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 59976208978 ps |
CPU time | 378.73 seconds |
Started | Jul 13 05:18:57 PM PDT 24 |
Finished | Jul 13 05:25:16 PM PDT 24 |
Peak memory | 249828 kb |
Host | smart-03217ebc-fcf5-427b-95f8-793b60c9bf7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990502098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1990502098 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_app/latest |
Test location | /workspace/coverage/default/34.kmac_burst_write.2404509829 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 89524167246 ps |
CPU time | 192.78 seconds |
Started | Jul 13 05:18:47 PM PDT 24 |
Finished | Jul 13 05:22:00 PM PDT 24 |
Peak memory | 228052 kb |
Host | smart-901d2d9d-6cce-4766-906e-5d33c5ec2212 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404509829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2404509829 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_burst_write/latest |
Test location | /workspace/coverage/default/34.kmac_entropy_refresh.3278431968 |
Short name | T1070 |
Test name | |
Test status | |
Simulation time | 11318592371 ps |
CPU time | 288.82 seconds |
Started | Jul 13 05:18:56 PM PDT 24 |
Finished | Jul 13 05:23:46 PM PDT 24 |
Peak memory | 249544 kb |
Host | smart-edf52fa7-20fd-416e-b064-07c3fe938f84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278431968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3278431968 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/34.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/34.kmac_error.1379864062 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 2433231262 ps |
CPU time | 188.8 seconds |
Started | Jul 13 05:18:56 PM PDT 24 |
Finished | Jul 13 05:22:05 PM PDT 24 |
Peak memory | 251296 kb |
Host | smart-89798663-be35-4514-8561-6bf18d276ae8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379864062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1379864062 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_error/latest |
Test location | /workspace/coverage/default/34.kmac_key_error.4088416260 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 1040805860 ps |
CPU time | 4.45 seconds |
Started | Jul 13 05:18:58 PM PDT 24 |
Finished | Jul 13 05:19:03 PM PDT 24 |
Peak memory | 222980 kb |
Host | smart-4dd19db6-feac-4bdc-a2c4-ebdebc1b1809 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088416260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.4088416260 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_key_error/latest |
Test location | /workspace/coverage/default/34.kmac_lc_escalation.2507690929 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 36280832 ps |
CPU time | 1.31 seconds |
Started | Jul 13 05:19:06 PM PDT 24 |
Finished | Jul 13 05:19:08 PM PDT 24 |
Peak memory | 226548 kb |
Host | smart-c3ed84c7-ef7d-4249-b547-443192508e1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507690929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2507690929 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/34.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/34.kmac_long_msg_and_output.3390586771 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 7188653734 ps |
CPU time | 785.26 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:31:45 PM PDT 24 |
Peak memory | 293340 kb |
Host | smart-8696ac79-5875-4c1a-874a-79fdeaf1f649 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390586771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a nd_output.3390586771 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/34.kmac_sideload.1387167261 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 29996637515 ps |
CPU time | 394.11 seconds |
Started | Jul 13 05:18:46 PM PDT 24 |
Finished | Jul 13 05:25:22 PM PDT 24 |
Peak memory | 249020 kb |
Host | smart-07c58126-6cd5-401e-ad8b-d3ac58eb5228 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387167261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1387167261 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_sideload/latest |
Test location | /workspace/coverage/default/34.kmac_smoke.3389823741 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 4930377707 ps |
CPU time | 14.26 seconds |
Started | Jul 13 05:18:39 PM PDT 24 |
Finished | Jul 13 05:18:54 PM PDT 24 |
Peak memory | 222752 kb |
Host | smart-c7965595-1174-46f8-b31d-5ded63ddc39c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389823741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3389823741 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_smoke/latest |
Test location | /workspace/coverage/default/34.kmac_stress_all.2377354101 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 74584561836 ps |
CPU time | 1302.64 seconds |
Started | Jul 13 05:19:09 PM PDT 24 |
Finished | Jul 13 05:40:52 PM PDT 24 |
Peak memory | 358352 kb |
Host | smart-cbbffd81-d30b-4f7c-9b9e-68eff79497de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2377354101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2377354101 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_stress_all/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_kmac.1396762886 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 93009253 ps |
CPU time | 5.4 seconds |
Started | Jul 13 05:18:56 PM PDT 24 |
Finished | Jul 13 05:19:01 PM PDT 24 |
Peak memory | 218456 kb |
Host | smart-0d4a5259-b3c6-4e7b-abac-79e51260506b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396762886 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.1396762886 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.236512485 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 118564071 ps |
CPU time | 5.36 seconds |
Started | Jul 13 05:18:58 PM PDT 24 |
Finished | Jul 13 05:19:04 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-32f1300c-1c2c-4330-8685-f1532c61120f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236512485 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 34.kmac_test_vectors_kmac_xof.236512485 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2632577606 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 186054617793 ps |
CPU time | 2225.35 seconds |
Started | Jul 13 05:18:48 PM PDT 24 |
Finished | Jul 13 05:55:53 PM PDT 24 |
Peak memory | 379520 kb |
Host | smart-68987a39-1d2d-4e2c-9fdb-ab53000de5bc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2632577606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2632577606 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_256.2861474324 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 19778083635 ps |
CPU time | 1930.91 seconds |
Started | Jul 13 05:18:46 PM PDT 24 |
Finished | Jul 13 05:50:57 PM PDT 24 |
Peak memory | 391572 kb |
Host | smart-f8d33f91-f46a-4c2d-b9a7-09cef7a843a8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2861474324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2861474324 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_384.172508107 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 144935383403 ps |
CPU time | 1916.82 seconds |
Started | Jul 13 05:18:49 PM PDT 24 |
Finished | Jul 13 05:50:47 PM PDT 24 |
Peak memory | 342004 kb |
Host | smart-5a1a6f73-44fb-4955-bc65-4b056d37692e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=172508107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.172508107 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_512.669157035 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 39562512560 ps |
CPU time | 1176.49 seconds |
Started | Jul 13 05:18:56 PM PDT 24 |
Finished | Jul 13 05:38:34 PM PDT 24 |
Peak memory | 303960 kb |
Host | smart-1b63ba7d-656b-4220-a1f5-19d7c99ce4a0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=669157035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.669157035 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_shake_128.2435992458 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 266216109356 ps |
CPU time | 5015.81 seconds |
Started | Jul 13 05:18:56 PM PDT 24 |
Finished | Jul 13 06:42:33 PM PDT 24 |
Peak memory | 662252 kb |
Host | smart-f18c1554-6c74-4be6-8b02-ae3b1c32e50e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2435992458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.2435992458 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/34.kmac_test_vectors_shake_256.300089800 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 695457014302 ps |
CPU time | 5079.64 seconds |
Started | Jul 13 05:18:55 PM PDT 24 |
Finished | Jul 13 06:43:35 PM PDT 24 |
Peak memory | 576976 kb |
Host | smart-0ca6bd35-1c71-4054-ac6c-c3f148dfe773 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=300089800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.300089800 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/34.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/35.kmac_alert_test.2669164965 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 44570202 ps |
CPU time | 0.89 seconds |
Started | Jul 13 05:19:24 PM PDT 24 |
Finished | Jul 13 05:19:25 PM PDT 24 |
Peak memory | 218292 kb |
Host | smart-188d84fe-af6a-4710-867b-2ecd587647bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669164965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2669164965 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_alert_test/latest |
Test location | /workspace/coverage/default/35.kmac_app.426010714 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 17199065776 ps |
CPU time | 289.57 seconds |
Started | Jul 13 05:19:13 PM PDT 24 |
Finished | Jul 13 05:24:03 PM PDT 24 |
Peak memory | 247736 kb |
Host | smart-edd55610-97f2-4f62-a788-0a81b8cce81e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426010714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.426010714 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_app/latest |
Test location | /workspace/coverage/default/35.kmac_burst_write.972680373 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 16117807447 ps |
CPU time | 529.65 seconds |
Started | Jul 13 05:19:06 PM PDT 24 |
Finished | Jul 13 05:27:56 PM PDT 24 |
Peak memory | 241032 kb |
Host | smart-f56b1dc8-7258-4ab8-a63d-cfb2d3d60edd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=972680373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.972680373 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_burst_write/latest |
Test location | /workspace/coverage/default/35.kmac_entropy_refresh.1625846403 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 42112010009 ps |
CPU time | 225.28 seconds |
Started | Jul 13 05:19:23 PM PDT 24 |
Finished | Jul 13 05:23:08 PM PDT 24 |
Peak memory | 244212 kb |
Host | smart-cf98b061-c8b4-4bec-bdf9-8af12eb6796b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625846403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1625846403 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/35.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/35.kmac_error.2051031600 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 29461722946 ps |
CPU time | 221.03 seconds |
Started | Jul 13 05:19:23 PM PDT 24 |
Finished | Jul 13 05:23:05 PM PDT 24 |
Peak memory | 251560 kb |
Host | smart-0c3f627b-b3b0-4ecf-bb60-d881b97c482e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051031600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2051031600 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_error/latest |
Test location | /workspace/coverage/default/35.kmac_key_error.775814832 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 1020873112 ps |
CPU time | 7.86 seconds |
Started | Jul 13 05:19:23 PM PDT 24 |
Finished | Jul 13 05:19:31 PM PDT 24 |
Peak memory | 223404 kb |
Host | smart-0ebba669-5903-44fc-a0d4-a1d710d5648c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775814832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.775814832 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_key_error/latest |
Test location | /workspace/coverage/default/35.kmac_lc_escalation.3910273149 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 157786128 ps |
CPU time | 1.41 seconds |
Started | Jul 13 05:19:24 PM PDT 24 |
Finished | Jul 13 05:19:25 PM PDT 24 |
Peak memory | 226604 kb |
Host | smart-9c3c3ab7-52f3-4725-94f8-7797923452ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910273149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3910273149 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/35.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/35.kmac_long_msg_and_output.2531972268 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 93972432416 ps |
CPU time | 813.31 seconds |
Started | Jul 13 05:19:06 PM PDT 24 |
Finished | Jul 13 05:32:40 PM PDT 24 |
Peak memory | 290096 kb |
Host | smart-25ac66fe-b5bb-4b1e-9682-14efede936fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531972268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.2531972268 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/35.kmac_sideload.2727351858 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 11690412160 ps |
CPU time | 99.41 seconds |
Started | Jul 13 05:19:07 PM PDT 24 |
Finished | Jul 13 05:20:47 PM PDT 24 |
Peak memory | 232412 kb |
Host | smart-28fcb599-c608-44b4-8d14-49a22c6377f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727351858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2727351858 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_sideload/latest |
Test location | /workspace/coverage/default/35.kmac_smoke.764207200 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 16685247115 ps |
CPU time | 55.22 seconds |
Started | Jul 13 05:19:06 PM PDT 24 |
Finished | Jul 13 05:20:01 PM PDT 24 |
Peak memory | 226664 kb |
Host | smart-abaf6d2c-a833-44d8-9c4a-2bc11c07d550 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764207200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.764207200 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_smoke/latest |
Test location | /workspace/coverage/default/35.kmac_stress_all.3753056935 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 16568064048 ps |
CPU time | 1085.51 seconds |
Started | Jul 13 05:19:23 PM PDT 24 |
Finished | Jul 13 05:37:29 PM PDT 24 |
Peak memory | 338664 kb |
Host | smart-f45346b1-d522-4974-aa57-93807d49fabd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3753056935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3753056935 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_stress_all/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_kmac.3001604903 |
Short name | T1042 |
Test name | |
Test status | |
Simulation time | 888121522 ps |
CPU time | 6.1 seconds |
Started | Jul 13 05:19:14 PM PDT 24 |
Finished | Jul 13 05:19:21 PM PDT 24 |
Peak memory | 218492 kb |
Host | smart-a9899765-304b-4180-9325-406f9455c127 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001604903 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.3001604903 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1023704645 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 98995954 ps |
CPU time | 5.74 seconds |
Started | Jul 13 05:19:17 PM PDT 24 |
Finished | Jul 13 05:19:23 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-99725a34-bd9f-484d-b4c7-1726919b90b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023704645 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1023704645 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2196173276 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 198570150889 ps |
CPU time | 2216.96 seconds |
Started | Jul 13 05:19:07 PM PDT 24 |
Finished | Jul 13 05:56:04 PM PDT 24 |
Peak memory | 387784 kb |
Host | smart-276bae6b-fa9b-4bb9-8b15-387f1f6cb695 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2196173276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2196173276 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_256.3383503849 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 91375962307 ps |
CPU time | 2222.65 seconds |
Started | Jul 13 05:19:06 PM PDT 24 |
Finished | Jul 13 05:56:10 PM PDT 24 |
Peak memory | 385800 kb |
Host | smart-f9854243-4cfb-4e18-a446-80dcaa470ebe |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3383503849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3383503849 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_384.648408494 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 33493733805 ps |
CPU time | 1583.22 seconds |
Started | Jul 13 05:19:14 PM PDT 24 |
Finished | Jul 13 05:45:38 PM PDT 24 |
Peak memory | 341116 kb |
Host | smart-946c345d-0548-4c16-beb1-57e3a31e1dff |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=648408494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.648408494 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_512.3294169888 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 195934699373 ps |
CPU time | 1391.29 seconds |
Started | Jul 13 05:19:15 PM PDT 24 |
Finished | Jul 13 05:42:26 PM PDT 24 |
Peak memory | 298716 kb |
Host | smart-817cad10-cf8c-487d-8b93-0ee4e7360d7c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3294169888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.3294169888 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_shake_128.182063704 |
Short name | T1039 |
Test name | |
Test status | |
Simulation time | 352746682543 ps |
CPU time | 5430.2 seconds |
Started | Jul 13 05:19:14 PM PDT 24 |
Finished | Jul 13 06:49:45 PM PDT 24 |
Peak memory | 661096 kb |
Host | smart-e70f2d17-d94a-4d2e-adf3-dfd0091ec272 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=182063704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.182063704 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/35.kmac_test_vectors_shake_256.4264277655 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 280493322455 ps |
CPU time | 4644.51 seconds |
Started | Jul 13 05:19:17 PM PDT 24 |
Finished | Jul 13 06:36:42 PM PDT 24 |
Peak memory | 576304 kb |
Host | smart-9e465003-ae27-46e6-a9f7-5935e27a952f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4264277655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.4264277655 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/35.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/36.kmac_alert_test.3589714027 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 51900126 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:19:53 PM PDT 24 |
Finished | Jul 13 05:19:54 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-602ba8bd-9c55-4a73-bf5e-e70a8b01f7d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589714027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3589714027 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_alert_test/latest |
Test location | /workspace/coverage/default/36.kmac_app.181371562 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 249874359 ps |
CPU time | 1.52 seconds |
Started | Jul 13 05:19:48 PM PDT 24 |
Finished | Jul 13 05:19:50 PM PDT 24 |
Peak memory | 225592 kb |
Host | smart-3712dbb1-4aee-4ec6-b1a2-7e0c321b04a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181371562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.181371562 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_app/latest |
Test location | /workspace/coverage/default/36.kmac_burst_write.1153059637 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 170563693706 ps |
CPU time | 1392.14 seconds |
Started | Jul 13 05:19:33 PM PDT 24 |
Finished | Jul 13 05:42:46 PM PDT 24 |
Peak memory | 240492 kb |
Host | smart-8fe9d09e-eac7-48bd-88c5-9744a85aed22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153059637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1153059637 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_burst_write/latest |
Test location | /workspace/coverage/default/36.kmac_entropy_refresh.1554494522 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2329471189 ps |
CPU time | 90.71 seconds |
Started | Jul 13 05:19:49 PM PDT 24 |
Finished | Jul 13 05:21:20 PM PDT 24 |
Peak memory | 231564 kb |
Host | smart-7f6b90f0-aaaf-4098-8750-fbbdd828d2b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554494522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1554494522 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/36.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/36.kmac_error.1468836491 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 3193332517 ps |
CPU time | 99.67 seconds |
Started | Jul 13 05:19:49 PM PDT 24 |
Finished | Jul 13 05:21:29 PM PDT 24 |
Peak memory | 241452 kb |
Host | smart-7ad7446f-c444-45e9-9cfd-71ad48f9fc2b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468836491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1468836491 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_error/latest |
Test location | /workspace/coverage/default/36.kmac_key_error.3816087261 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 793320551 ps |
CPU time | 4.92 seconds |
Started | Jul 13 05:19:49 PM PDT 24 |
Finished | Jul 13 05:19:55 PM PDT 24 |
Peak memory | 222848 kb |
Host | smart-d985e7e9-0f3a-4a88-b954-2ed0b505b864 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816087261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3816087261 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_key_error/latest |
Test location | /workspace/coverage/default/36.kmac_lc_escalation.306554323 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 52943584 ps |
CPU time | 1.26 seconds |
Started | Jul 13 05:19:50 PM PDT 24 |
Finished | Jul 13 05:19:52 PM PDT 24 |
Peak memory | 226580 kb |
Host | smart-f52fff8d-2b66-4724-bab4-8570f7e75bc9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306554323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.306554323 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/36.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/36.kmac_long_msg_and_output.208947957 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 20882702007 ps |
CPU time | 2285.78 seconds |
Started | Jul 13 05:19:25 PM PDT 24 |
Finished | Jul 13 05:57:31 PM PDT 24 |
Peak memory | 404520 kb |
Host | smart-b4a3b879-68fe-42d4-b190-07e008d3f95d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208947957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an d_output.208947957 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/36.kmac_sideload.2065437090 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 17550692596 ps |
CPU time | 292.83 seconds |
Started | Jul 13 05:19:34 PM PDT 24 |
Finished | Jul 13 05:24:27 PM PDT 24 |
Peak memory | 246036 kb |
Host | smart-7db061d0-b20b-47d5-9a53-c10b2a59e565 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065437090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2065437090 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_sideload/latest |
Test location | /workspace/coverage/default/36.kmac_smoke.4127624015 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 1319098097 ps |
CPU time | 10.77 seconds |
Started | Jul 13 05:19:23 PM PDT 24 |
Finished | Jul 13 05:19:35 PM PDT 24 |
Peak memory | 219436 kb |
Host | smart-701c0a69-3cac-47c0-b930-ffdcda870491 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127624015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.4127624015 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_smoke/latest |
Test location | /workspace/coverage/default/36.kmac_stress_all.3610643180 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 11767250398 ps |
CPU time | 250.33 seconds |
Started | Jul 13 05:19:55 PM PDT 24 |
Finished | Jul 13 05:24:05 PM PDT 24 |
Peak memory | 245904 kb |
Host | smart-4e945c6f-d755-468d-83dd-729123b285fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3610643180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3610643180 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_stress_all/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_kmac.383235285 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 517226034 ps |
CPU time | 5.92 seconds |
Started | Jul 13 05:19:48 PM PDT 24 |
Finished | Jul 13 05:19:54 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-db4e3bd8-ce5f-4c73-bcc0-9f8a560956d0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383235285 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.kmac_test_vectors_kmac.383235285 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.99915356 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 268907675 ps |
CPU time | 6.76 seconds |
Started | Jul 13 05:19:49 PM PDT 24 |
Finished | Jul 13 05:19:56 PM PDT 24 |
Peak memory | 219356 kb |
Host | smart-500370ec-6913-475f-8b12-ac3ca9468e83 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99915356 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.kmac_test_vectors_kmac_xof.99915356 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_224.3938849974 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 67354961387 ps |
CPU time | 2176.61 seconds |
Started | Jul 13 05:19:34 PM PDT 24 |
Finished | Jul 13 05:55:51 PM PDT 24 |
Peak memory | 407852 kb |
Host | smart-a5c3d307-98b2-4503-af48-09af4fa5babc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3938849974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3938849974 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2016625024 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 256898298720 ps |
CPU time | 2158.5 seconds |
Started | Jul 13 05:19:32 PM PDT 24 |
Finished | Jul 13 05:55:32 PM PDT 24 |
Peak memory | 385260 kb |
Host | smart-19f8619f-5c0f-40ee-a018-5ba488c0f968 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2016625024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2016625024 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_384.3808040494 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 152482752985 ps |
CPU time | 1829.99 seconds |
Started | Jul 13 05:19:33 PM PDT 24 |
Finished | Jul 13 05:50:04 PM PDT 24 |
Peak memory | 338936 kb |
Host | smart-02e4cb7c-7ccd-4e24-bfb3-906ef1ff7cc9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3808040494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3808040494 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_512.2216783184 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 44607652387 ps |
CPU time | 1196.31 seconds |
Started | Jul 13 05:19:32 PM PDT 24 |
Finished | Jul 13 05:39:29 PM PDT 24 |
Peak memory | 301136 kb |
Host | smart-5cb4413e-c74b-4b2a-842b-35530397c096 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2216783184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2216783184 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_shake_128.2047656418 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 728533316126 ps |
CPU time | 5643.63 seconds |
Started | Jul 13 05:19:49 PM PDT 24 |
Finished | Jul 13 06:53:53 PM PDT 24 |
Peak memory | 652592 kb |
Host | smart-2ebcfd37-ccc4-42f2-93ef-1739ca08dede |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2047656418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2047656418 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/36.kmac_test_vectors_shake_256.1732908216 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 1005059755735 ps |
CPU time | 4882.13 seconds |
Started | Jul 13 05:19:48 PM PDT 24 |
Finished | Jul 13 06:41:10 PM PDT 24 |
Peak memory | 571644 kb |
Host | smart-957c2119-b51b-4f91-ba42-194a3fdc6347 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1732908216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1732908216 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/36.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/37.kmac_alert_test.253957621 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 56305131 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:20:13 PM PDT 24 |
Finished | Jul 13 05:20:14 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-81c90ef5-8d44-41e0-b062-2aad262d8002 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253957621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.253957621 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_alert_test/latest |
Test location | /workspace/coverage/default/37.kmac_app.2503883609 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 45740079527 ps |
CPU time | 285.18 seconds |
Started | Jul 13 05:20:08 PM PDT 24 |
Finished | Jul 13 05:24:53 PM PDT 24 |
Peak memory | 245780 kb |
Host | smart-b9e1458e-f857-4772-8645-7eb30fd53ac4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503883609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2503883609 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_app/latest |
Test location | /workspace/coverage/default/37.kmac_burst_write.3650398918 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 8272471622 ps |
CPU time | 87.28 seconds |
Started | Jul 13 05:19:55 PM PDT 24 |
Finished | Jul 13 05:21:22 PM PDT 24 |
Peak memory | 234788 kb |
Host | smart-0f6f0fb5-56e8-4cc7-9d8c-21df7f2a101e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650398918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3650398918 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_burst_write/latest |
Test location | /workspace/coverage/default/37.kmac_entropy_refresh.1524411853 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 92805749620 ps |
CPU time | 151.12 seconds |
Started | Jul 13 05:20:04 PM PDT 24 |
Finished | Jul 13 05:22:35 PM PDT 24 |
Peak memory | 243048 kb |
Host | smart-4566f263-e495-4311-a918-db1e65f79935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524411853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1524411853 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/37.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/37.kmac_error.750141352 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 7487380631 ps |
CPU time | 292.95 seconds |
Started | Jul 13 05:20:04 PM PDT 24 |
Finished | Jul 13 05:24:57 PM PDT 24 |
Peak memory | 259164 kb |
Host | smart-ba61cbdb-121b-4dce-afa1-5cfb1bc8393b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750141352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.750141352 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_error/latest |
Test location | /workspace/coverage/default/37.kmac_key_error.1687634066 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 1587803764 ps |
CPU time | 11.69 seconds |
Started | Jul 13 05:20:13 PM PDT 24 |
Finished | Jul 13 05:20:25 PM PDT 24 |
Peak memory | 224704 kb |
Host | smart-6e3556fe-721f-4b57-bda4-3c767d0516e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687634066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1687634066 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_key_error/latest |
Test location | /workspace/coverage/default/37.kmac_lc_escalation.832830068 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 43858747 ps |
CPU time | 1.43 seconds |
Started | Jul 13 05:20:17 PM PDT 24 |
Finished | Jul 13 05:20:19 PM PDT 24 |
Peak memory | 226516 kb |
Host | smart-772a1e27-f848-4154-a329-75ab580582d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832830068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.832830068 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/37.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/37.kmac_long_msg_and_output.4033751189 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 515023135615 ps |
CPU time | 3078.3 seconds |
Started | Jul 13 05:19:54 PM PDT 24 |
Finished | Jul 13 06:11:13 PM PDT 24 |
Peak memory | 457968 kb |
Host | smart-b4a06305-d829-4102-9d26-e8be1d55e301 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033751189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.4033751189 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/37.kmac_sideload.1739753150 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 41138519531 ps |
CPU time | 339.1 seconds |
Started | Jul 13 05:19:53 PM PDT 24 |
Finished | Jul 13 05:25:32 PM PDT 24 |
Peak memory | 247284 kb |
Host | smart-5c885b81-1e21-4abd-9a50-f3a412f26e03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739753150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1739753150 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_sideload/latest |
Test location | /workspace/coverage/default/37.kmac_smoke.922768538 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 4313300837 ps |
CPU time | 24.01 seconds |
Started | Jul 13 05:19:53 PM PDT 24 |
Finished | Jul 13 05:20:17 PM PDT 24 |
Peak memory | 222968 kb |
Host | smart-06f5cd98-d973-4fcf-93eb-b10922dbefc4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922768538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.922768538 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_smoke/latest |
Test location | /workspace/coverage/default/37.kmac_stress_all.2119671620 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 41967704684 ps |
CPU time | 1387.8 seconds |
Started | Jul 13 05:20:12 PM PDT 24 |
Finished | Jul 13 05:43:21 PM PDT 24 |
Peak memory | 358088 kb |
Host | smart-29512b6e-c3af-4d01-bfb8-37a1b392f32f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2119671620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2119671620 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_stress_all/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_kmac.4173492603 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 840244192 ps |
CPU time | 6.07 seconds |
Started | Jul 13 05:20:04 PM PDT 24 |
Finished | Jul 13 05:20:10 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-b7515f3c-5164-456c-9403-abcc9a7205a1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173492603 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.4173492603 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2156093004 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 848757734 ps |
CPU time | 6.01 seconds |
Started | Jul 13 05:20:03 PM PDT 24 |
Finished | Jul 13 05:20:10 PM PDT 24 |
Peak memory | 218748 kb |
Host | smart-1718883a-7015-4949-97d6-0357051cbb10 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156093004 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2156093004 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2307937448 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 39432788714 ps |
CPU time | 2004.19 seconds |
Started | Jul 13 05:19:51 PM PDT 24 |
Finished | Jul 13 05:53:16 PM PDT 24 |
Peak memory | 393732 kb |
Host | smart-9de6c280-e92a-43fc-bbe8-8cf92b44ff2c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2307937448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2307937448 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_256.3940491620 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 297069869388 ps |
CPU time | 2141.9 seconds |
Started | Jul 13 05:19:56 PM PDT 24 |
Finished | Jul 13 05:55:38 PM PDT 24 |
Peak memory | 390052 kb |
Host | smart-1c923e76-0c75-4227-868a-de33aa15eb4e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3940491620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.3940491620 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2540068727 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 66921117553 ps |
CPU time | 1564.43 seconds |
Started | Jul 13 05:19:53 PM PDT 24 |
Finished | Jul 13 05:45:58 PM PDT 24 |
Peak memory | 339276 kb |
Host | smart-2cd9b50b-aa60-4748-94a1-d24e8ea96438 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2540068727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2540068727 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_512.719978121 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 37159475549 ps |
CPU time | 1244.06 seconds |
Started | Jul 13 05:20:03 PM PDT 24 |
Finished | Jul 13 05:40:47 PM PDT 24 |
Peak memory | 298248 kb |
Host | smart-6d26b3f4-c01a-4b38-82c9-b30afb138102 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=719978121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.719978121 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_shake_128.2814845293 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 369685779098 ps |
CPU time | 5594.47 seconds |
Started | Jul 13 05:20:02 PM PDT 24 |
Finished | Jul 13 06:53:17 PM PDT 24 |
Peak memory | 673180 kb |
Host | smart-1f837c8d-1c93-4838-ae9a-3045ff3797e4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2814845293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.2814845293 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/37.kmac_test_vectors_shake_256.555137678 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 1170009926091 ps |
CPU time | 5350.93 seconds |
Started | Jul 13 05:20:03 PM PDT 24 |
Finished | Jul 13 06:49:14 PM PDT 24 |
Peak memory | 577448 kb |
Host | smart-15498df0-ee3b-45ff-afd6-ba74723cc0d3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=555137678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.555137678 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/37.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/38.kmac_alert_test.4068621595 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 32326324 ps |
CPU time | 0.75 seconds |
Started | Jul 13 05:20:39 PM PDT 24 |
Finished | Jul 13 05:20:40 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-77769fcb-ab59-4582-a090-80bcf48346f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068621595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4068621595 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_alert_test/latest |
Test location | /workspace/coverage/default/38.kmac_app.764794199 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 31645295344 ps |
CPU time | 312.08 seconds |
Started | Jul 13 05:20:31 PM PDT 24 |
Finished | Jul 13 05:25:44 PM PDT 24 |
Peak memory | 245916 kb |
Host | smart-e9451659-fa98-4c51-93cd-56c04d539066 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764794199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.764794199 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_app/latest |
Test location | /workspace/coverage/default/38.kmac_burst_write.3215672373 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 3390698506 ps |
CPU time | 40.08 seconds |
Started | Jul 13 05:20:23 PM PDT 24 |
Finished | Jul 13 05:21:04 PM PDT 24 |
Peak memory | 224848 kb |
Host | smart-b0d60e02-4ee7-42ee-ae8d-aa85d0c1a999 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215672373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3215672373 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_burst_write/latest |
Test location | /workspace/coverage/default/38.kmac_entropy_refresh.1479062611 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 112505026 ps |
CPU time | 2.06 seconds |
Started | Jul 13 05:20:32 PM PDT 24 |
Finished | Jul 13 05:20:34 PM PDT 24 |
Peak memory | 225752 kb |
Host | smart-cc135997-e282-4bcd-a0b8-e1d0be380b48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479062611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1479062611 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/38.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/38.kmac_error.220530148 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 18307181161 ps |
CPU time | 100.66 seconds |
Started | Jul 13 05:20:31 PM PDT 24 |
Finished | Jul 13 05:22:12 PM PDT 24 |
Peak memory | 243056 kb |
Host | smart-b5c3ae45-2eae-4e6c-a5be-d5455f7075c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220530148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.220530148 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_error/latest |
Test location | /workspace/coverage/default/38.kmac_key_error.1875903206 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 1314901931 ps |
CPU time | 6.37 seconds |
Started | Jul 13 05:20:32 PM PDT 24 |
Finished | Jul 13 05:20:38 PM PDT 24 |
Peak memory | 223304 kb |
Host | smart-918a7808-39e3-479a-b391-474dd8d8291e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875903206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1875903206 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_key_error/latest |
Test location | /workspace/coverage/default/38.kmac_lc_escalation.3697665431 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 132066411 ps |
CPU time | 1.3 seconds |
Started | Jul 13 05:20:33 PM PDT 24 |
Finished | Jul 13 05:20:34 PM PDT 24 |
Peak memory | 226472 kb |
Host | smart-75962cba-ecc8-48cb-bab1-402c0c1f8e87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697665431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3697665431 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/38.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/38.kmac_long_msg_and_output.1132412463 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 11525799548 ps |
CPU time | 1227.76 seconds |
Started | Jul 13 05:20:17 PM PDT 24 |
Finished | Jul 13 05:40:46 PM PDT 24 |
Peak memory | 323540 kb |
Host | smart-c801ce2d-41b0-4820-a1e6-c8d9615e9211 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132412463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.1132412463 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/38.kmac_sideload.2747182924 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 10820740648 ps |
CPU time | 269.87 seconds |
Started | Jul 13 05:20:27 PM PDT 24 |
Finished | Jul 13 05:24:57 PM PDT 24 |
Peak memory | 243204 kb |
Host | smart-e971e4df-029d-46e8-ad7e-a267fe214933 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747182924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2747182924 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_sideload/latest |
Test location | /workspace/coverage/default/38.kmac_smoke.2367388384 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 982056084 ps |
CPU time | 40.3 seconds |
Started | Jul 13 05:20:12 PM PDT 24 |
Finished | Jul 13 05:20:53 PM PDT 24 |
Peak memory | 219260 kb |
Host | smart-3f90606c-ac20-41f7-8ec6-aa123303d968 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367388384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2367388384 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_smoke/latest |
Test location | /workspace/coverage/default/38.kmac_stress_all.4007026187 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 7651729171 ps |
CPU time | 39.89 seconds |
Started | Jul 13 05:20:39 PM PDT 24 |
Finished | Jul 13 05:21:19 PM PDT 24 |
Peak memory | 225240 kb |
Host | smart-d611aa3c-2f41-455c-9864-1c2ce2b13446 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4007026187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.4007026187 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_stress_all/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_kmac.1814891490 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 211797884 ps |
CPU time | 6.21 seconds |
Started | Jul 13 05:20:32 PM PDT 24 |
Finished | Jul 13 05:20:38 PM PDT 24 |
Peak memory | 219536 kb |
Host | smart-a3a07bf5-a83c-4d1f-8efb-f7b3841a2419 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814891490 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.1814891490 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.3309118674 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 225502784 ps |
CPU time | 6.44 seconds |
Started | Jul 13 05:20:34 PM PDT 24 |
Finished | Jul 13 05:20:40 PM PDT 24 |
Peak memory | 218768 kb |
Host | smart-0be5a400-4f1e-49a7-92d0-7846f7562504 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309118674 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.3309118674 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1831134486 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 1092548463060 ps |
CPU time | 2538.08 seconds |
Started | Jul 13 05:20:22 PM PDT 24 |
Finished | Jul 13 06:02:41 PM PDT 24 |
Peak memory | 396512 kb |
Host | smart-14794376-d023-4801-9c71-dc1371a83e20 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1831134486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1831134486 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_256.4162827656 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 35777224184 ps |
CPU time | 1831.27 seconds |
Started | Jul 13 05:20:22 PM PDT 24 |
Finished | Jul 13 05:50:54 PM PDT 24 |
Peak memory | 389576 kb |
Host | smart-5ae052e5-8706-4bf4-8348-524f000c7cbc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4162827656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.4162827656 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_384.489278675 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 60542365084 ps |
CPU time | 1444.2 seconds |
Started | Jul 13 05:20:27 PM PDT 24 |
Finished | Jul 13 05:44:32 PM PDT 24 |
Peak memory | 343160 kb |
Host | smart-2dd5e627-97ba-4276-98c1-412809ae1442 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=489278675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.489278675 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3934765878 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 35391166879 ps |
CPU time | 1231.09 seconds |
Started | Jul 13 05:20:27 PM PDT 24 |
Finished | Jul 13 05:40:59 PM PDT 24 |
Peak memory | 304020 kb |
Host | smart-66c9e6f9-3907-4456-84bf-6461e6079c97 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3934765878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3934765878 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_shake_128.226242586 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 781119290257 ps |
CPU time | 5804.82 seconds |
Started | Jul 13 05:20:32 PM PDT 24 |
Finished | Jul 13 06:57:17 PM PDT 24 |
Peak memory | 656176 kb |
Host | smart-78b803b3-dbff-4ef4-af88-6c750e52e719 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=226242586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.226242586 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/38.kmac_test_vectors_shake_256.4232411169 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 1000440122085 ps |
CPU time | 4908.77 seconds |
Started | Jul 13 05:20:30 PM PDT 24 |
Finished | Jul 13 06:42:20 PM PDT 24 |
Peak memory | 573116 kb |
Host | smart-141527a6-317e-4399-b1d1-52c77e907ce3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4232411169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.4232411169 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/38.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/39.kmac_alert_test.1326368201 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 17873965 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:20:55 PM PDT 24 |
Finished | Jul 13 05:20:56 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-70d1a63b-81e6-4183-9bdd-1030f1b70a73 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326368201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1326368201 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_alert_test/latest |
Test location | /workspace/coverage/default/39.kmac_app.2252203043 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 1733276408 ps |
CPU time | 53.61 seconds |
Started | Jul 13 05:20:51 PM PDT 24 |
Finished | Jul 13 05:21:45 PM PDT 24 |
Peak memory | 227240 kb |
Host | smart-d33d55bd-6665-44fe-b98b-a019d7f6b131 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252203043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2252203043 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_app/latest |
Test location | /workspace/coverage/default/39.kmac_burst_write.1570622621 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 114791981762 ps |
CPU time | 1120.2 seconds |
Started | Jul 13 05:20:40 PM PDT 24 |
Finished | Jul 13 05:39:21 PM PDT 24 |
Peak memory | 243064 kb |
Host | smart-ca8dd9c0-472c-4d6e-b263-e420522bfdb6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570622621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1570622621 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_burst_write/latest |
Test location | /workspace/coverage/default/39.kmac_entropy_refresh.282035682 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 13972707477 ps |
CPU time | 295.96 seconds |
Started | Jul 13 05:20:58 PM PDT 24 |
Finished | Jul 13 05:25:54 PM PDT 24 |
Peak memory | 246332 kb |
Host | smart-de07205a-8514-41cd-b07a-06569b30e8db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282035682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.282035682 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/39.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/39.kmac_error.3554889441 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 24625593195 ps |
CPU time | 395.31 seconds |
Started | Jul 13 05:20:56 PM PDT 24 |
Finished | Jul 13 05:27:32 PM PDT 24 |
Peak memory | 259436 kb |
Host | smart-48daa75c-a625-419a-a001-e5abfae8b258 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554889441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3554889441 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_error/latest |
Test location | /workspace/coverage/default/39.kmac_key_error.1463544502 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 764893644 ps |
CPU time | 6.42 seconds |
Started | Jul 13 05:20:55 PM PDT 24 |
Finished | Jul 13 05:21:01 PM PDT 24 |
Peak memory | 224208 kb |
Host | smart-c69c62af-1fc4-48d8-8f77-52127280e04c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463544502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1463544502 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_key_error/latest |
Test location | /workspace/coverage/default/39.kmac_lc_escalation.2246162997 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 68589780 ps |
CPU time | 1.37 seconds |
Started | Jul 13 05:20:58 PM PDT 24 |
Finished | Jul 13 05:20:59 PM PDT 24 |
Peak memory | 226560 kb |
Host | smart-66c3c488-a71a-422e-b79a-35d75bf82c95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246162997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2246162997 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/39.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/39.kmac_long_msg_and_output.2856860242 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 36263986512 ps |
CPU time | 2040.22 seconds |
Started | Jul 13 05:20:39 PM PDT 24 |
Finished | Jul 13 05:54:40 PM PDT 24 |
Peak memory | 390604 kb |
Host | smart-281cc2c6-ddef-4b69-af15-6e6dcea0dc63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856860242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.2856860242 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/39.kmac_sideload.3158619372 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 4400532150 ps |
CPU time | 37.92 seconds |
Started | Jul 13 05:20:40 PM PDT 24 |
Finished | Jul 13 05:21:18 PM PDT 24 |
Peak memory | 226592 kb |
Host | smart-11830521-c715-46d4-8da5-2fba53853169 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158619372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3158619372 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_sideload/latest |
Test location | /workspace/coverage/default/39.kmac_smoke.1835032076 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1726727085 ps |
CPU time | 42.61 seconds |
Started | Jul 13 05:20:40 PM PDT 24 |
Finished | Jul 13 05:21:23 PM PDT 24 |
Peak memory | 225984 kb |
Host | smart-aea2fdc8-e120-48e5-bc58-d4fd65a4b996 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835032076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1835032076 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_smoke/latest |
Test location | /workspace/coverage/default/39.kmac_stress_all.304051092 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 19617340795 ps |
CPU time | 255.01 seconds |
Started | Jul 13 05:20:57 PM PDT 24 |
Finished | Jul 13 05:25:12 PM PDT 24 |
Peak memory | 229392 kb |
Host | smart-4bc7acf8-7a95-4c47-91ee-db8c4c073d93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=304051092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.304051092 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_stress_all/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_kmac.1652884700 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 127382065 ps |
CPU time | 6.04 seconds |
Started | Jul 13 05:20:48 PM PDT 24 |
Finished | Jul 13 05:20:54 PM PDT 24 |
Peak memory | 219444 kb |
Host | smart-b4155da9-d29e-4f6b-82ef-9a5a1e6db4a5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652884700 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.1652884700 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3180851107 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 352354632 ps |
CPU time | 6.15 seconds |
Started | Jul 13 05:20:48 PM PDT 24 |
Finished | Jul 13 05:20:54 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-fa7e29d6-d042-44ee-a0e7-e861d8523d87 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180851107 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3180851107 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_224.4073865245 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 21276121074 ps |
CPU time | 1981.04 seconds |
Started | Jul 13 05:20:40 PM PDT 24 |
Finished | Jul 13 05:53:42 PM PDT 24 |
Peak memory | 397616 kb |
Host | smart-439d1c8c-8f56-41be-a8bc-e4b9a2fcc7a5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4073865245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.4073865245 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_256.403575739 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 372727438976 ps |
CPU time | 2233.69 seconds |
Started | Jul 13 05:20:39 PM PDT 24 |
Finished | Jul 13 05:57:53 PM PDT 24 |
Peak memory | 395020 kb |
Host | smart-9df75bdd-0595-4696-8646-993f6f88499c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=403575739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.403575739 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3443651072 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 146757964078 ps |
CPU time | 1743 seconds |
Started | Jul 13 05:20:40 PM PDT 24 |
Finished | Jul 13 05:49:44 PM PDT 24 |
Peak memory | 338952 kb |
Host | smart-f8f2fe44-ed4e-4d3d-8cd2-d6151df50ae4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3443651072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3443651072 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_512.838412356 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 41951937294 ps |
CPU time | 1208.48 seconds |
Started | Jul 13 05:20:48 PM PDT 24 |
Finished | Jul 13 05:40:57 PM PDT 24 |
Peak memory | 300532 kb |
Host | smart-2bc89db5-a67a-43af-a83b-5dd297fd8998 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=838412356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.838412356 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_shake_128.1981682149 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 527509539591 ps |
CPU time | 5852.18 seconds |
Started | Jul 13 05:20:49 PM PDT 24 |
Finished | Jul 13 06:58:22 PM PDT 24 |
Peak memory | 649852 kb |
Host | smart-db3363c9-5009-4366-a870-de7d580b321c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1981682149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1981682149 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/39.kmac_test_vectors_shake_256.1258815824 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 235573324790 ps |
CPU time | 4383.93 seconds |
Started | Jul 13 05:20:49 PM PDT 24 |
Finished | Jul 13 06:33:54 PM PDT 24 |
Peak memory | 560304 kb |
Host | smart-3439f46d-0d5a-4070-9019-ac18a014be77 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1258815824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1258815824 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/39.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/4.kmac_alert_test.1331963537 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 34017420 ps |
CPU time | 0.87 seconds |
Started | Jul 13 05:06:35 PM PDT 24 |
Finished | Jul 13 05:06:36 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-08dcd2f6-d80f-4c5c-bb0d-2bd1906dae2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331963537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1331963537 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_alert_test/latest |
Test location | /workspace/coverage/default/4.kmac_app.1611141161 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 12044399834 ps |
CPU time | 171.44 seconds |
Started | Jul 13 05:06:22 PM PDT 24 |
Finished | Jul 13 05:09:14 PM PDT 24 |
Peak memory | 238620 kb |
Host | smart-e5b88c72-b9a9-410c-890f-c0156c840ae1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611141161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1611141161 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_app/latest |
Test location | /workspace/coverage/default/4.kmac_app_with_partial_data.2560644456 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 18584816422 ps |
CPU time | 409.88 seconds |
Started | Jul 13 05:06:24 PM PDT 24 |
Finished | Jul 13 05:13:14 PM PDT 24 |
Peak memory | 250580 kb |
Host | smart-9ddf9918-5a37-49fb-ad17-6523b4bf024f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560644456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2560644456 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/4.kmac_burst_write.3260286148 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 30786477212 ps |
CPU time | 1476.06 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:30:49 PM PDT 24 |
Peak memory | 237808 kb |
Host | smart-7152dc15-f6cd-49b0-ab0d-fdc2188a6a0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260286148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3260286148 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_burst_write/latest |
Test location | /workspace/coverage/default/4.kmac_edn_timeout_error.2916876988 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 91745862 ps |
CPU time | 1.06 seconds |
Started | Jul 13 05:06:22 PM PDT 24 |
Finished | Jul 13 05:06:24 PM PDT 24 |
Peak memory | 218164 kb |
Host | smart-14fd36a3-a7ab-4cd8-87ec-dc17a4e1a83d |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2916876988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2916876988 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/4.kmac_entropy_mode_error.3286922995 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 21920770 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:06:36 PM PDT 24 |
Finished | Jul 13 05:06:37 PM PDT 24 |
Peak memory | 218148 kb |
Host | smart-76d6a55d-6732-4e73-9c18-1b00776356dc |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3286922995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3286922995 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/4.kmac_entropy_refresh.4259651871 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 15331652611 ps |
CPU time | 152.59 seconds |
Started | Jul 13 05:06:22 PM PDT 24 |
Finished | Jul 13 05:08:55 PM PDT 24 |
Peak memory | 239140 kb |
Host | smart-6db60e9c-bdf9-436e-ae2b-4043b2e5db4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259651871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.4259651871 +enable_masking=1 +s w_key_masked=0 |
Directory | /workspace/4.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/4.kmac_error.2934679011 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 36446316670 ps |
CPU time | 332.95 seconds |
Started | Jul 13 05:06:22 PM PDT 24 |
Finished | Jul 13 05:11:55 PM PDT 24 |
Peak memory | 259484 kb |
Host | smart-9bebb51e-2b46-4b95-80a8-d1c8b13748bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934679011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2934679011 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_error/latest |
Test location | /workspace/coverage/default/4.kmac_lc_escalation.1002192994 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 100047752 ps |
CPU time | 1.36 seconds |
Started | Jul 13 05:06:34 PM PDT 24 |
Finished | Jul 13 05:06:36 PM PDT 24 |
Peak memory | 226488 kb |
Host | smart-1b4c34ae-54f2-4c44-90fa-4b426fa89cab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002192994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1002192994 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/4.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/4.kmac_long_msg_and_output.4103624304 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 34499309942 ps |
CPU time | 1820.16 seconds |
Started | Jul 13 05:06:13 PM PDT 24 |
Finished | Jul 13 05:36:34 PM PDT 24 |
Peak memory | 387248 kb |
Host | smart-a9ab222b-a115-49a4-8e8b-331f99582c73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103624304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.4103624304 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/4.kmac_mubi.2410496354 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 6688144897 ps |
CPU time | 154.92 seconds |
Started | Jul 13 05:06:23 PM PDT 24 |
Finished | Jul 13 05:08:59 PM PDT 24 |
Peak memory | 237740 kb |
Host | smart-e749ebbe-d8a8-4ed3-ad11-492b08bbab67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410496354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2410496354 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_mubi/latest |
Test location | /workspace/coverage/default/4.kmac_sideload.2947759100 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 13067664377 ps |
CPU time | 332.98 seconds |
Started | Jul 13 05:06:13 PM PDT 24 |
Finished | Jul 13 05:11:46 PM PDT 24 |
Peak memory | 249068 kb |
Host | smart-828d5511-59a8-4820-85ec-7bc20642f7f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947759100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2947759100 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_sideload/latest |
Test location | /workspace/coverage/default/4.kmac_smoke.2168661122 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 18657878318 ps |
CPU time | 93.84 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:07:46 PM PDT 24 |
Peak memory | 222868 kb |
Host | smart-18be69cf-6eda-4897-9e7e-da8d8b21f309 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168661122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2168661122 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_smoke/latest |
Test location | /workspace/coverage/default/4.kmac_stress_all.3452700904 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 66153749422 ps |
CPU time | 1514.25 seconds |
Started | Jul 13 05:06:36 PM PDT 24 |
Finished | Jul 13 05:31:51 PM PDT 24 |
Peak memory | 352276 kb |
Host | smart-35a5b175-acb0-4ec8-b3a6-9b4a16410a1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3452700904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3452700904 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_stress_all/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_kmac.725455729 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 231602580 ps |
CPU time | 5.37 seconds |
Started | Jul 13 05:06:23 PM PDT 24 |
Finished | Jul 13 05:06:29 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-7e45a8d9-f643-4280-800c-4f7eb1e86857 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725455729 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.kmac_test_vectors_kmac.725455729 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3571500596 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 157933399 ps |
CPU time | 5.97 seconds |
Started | Jul 13 05:06:24 PM PDT 24 |
Finished | Jul 13 05:06:31 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-61d4fca3-9597-4c1a-8936-bc8bad121954 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571500596 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3571500596 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_224.4074463338 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 20519825913 ps |
CPU time | 2067.33 seconds |
Started | Jul 13 05:06:12 PM PDT 24 |
Finished | Jul 13 05:40:41 PM PDT 24 |
Peak memory | 390140 kb |
Host | smart-fbe31db8-c2ff-4ceb-b899-e0fd12ac85bb |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4074463338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4074463338 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_256.3005664672 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 39490736980 ps |
CPU time | 2015.46 seconds |
Started | Jul 13 05:06:13 PM PDT 24 |
Finished | Jul 13 05:39:49 PM PDT 24 |
Peak memory | 394472 kb |
Host | smart-90c41850-cbff-4324-aa35-48b2591ea529 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3005664672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3005664672 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_384.111049052 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 95339038917 ps |
CPU time | 1644.33 seconds |
Started | Jul 13 05:06:14 PM PDT 24 |
Finished | Jul 13 05:33:39 PM PDT 24 |
Peak memory | 335000 kb |
Host | smart-c15c5512-1a3b-4cd5-ba14-75c85a23d718 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=111049052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.111049052 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2731828277 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 194276902550 ps |
CPU time | 1406.74 seconds |
Started | Jul 13 05:06:24 PM PDT 24 |
Finished | Jul 13 05:29:51 PM PDT 24 |
Peak memory | 298048 kb |
Host | smart-c275ddeb-ec73-415d-986d-ad0a6c1e8fde |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2731828277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2731828277 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_shake_128.725283511 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 258304552952 ps |
CPU time | 4810.68 seconds |
Started | Jul 13 05:06:23 PM PDT 24 |
Finished | Jul 13 06:26:35 PM PDT 24 |
Peak memory | 654984 kb |
Host | smart-f31430ba-da08-4695-94b2-5bbd83420a6f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=725283511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.725283511 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/4.kmac_test_vectors_shake_256.2493766472 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 583878271725 ps |
CPU time | 4096.59 seconds |
Started | Jul 13 05:06:23 PM PDT 24 |
Finished | Jul 13 06:14:41 PM PDT 24 |
Peak memory | 568904 kb |
Host | smart-6348fce5-7298-41a0-88d2-dff24d6d8478 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2493766472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2493766472 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/4.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/40.kmac_alert_test.1751756168 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 67894059 ps |
CPU time | 0.88 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:21:27 PM PDT 24 |
Peak memory | 218188 kb |
Host | smart-f0171004-1c88-4c82-a8f0-2029a0341ca8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751756168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1751756168 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_alert_test/latest |
Test location | /workspace/coverage/default/40.kmac_app.1860971667 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 8924230141 ps |
CPU time | 231.88 seconds |
Started | Jul 13 05:21:16 PM PDT 24 |
Finished | Jul 13 05:25:08 PM PDT 24 |
Peak memory | 241664 kb |
Host | smart-fa60d188-a527-424a-9083-ce1915d119ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860971667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1860971667 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_app/latest |
Test location | /workspace/coverage/default/40.kmac_burst_write.1231948988 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 48438640394 ps |
CPU time | 726.61 seconds |
Started | Jul 13 05:21:06 PM PDT 24 |
Finished | Jul 13 05:33:13 PM PDT 24 |
Peak memory | 243048 kb |
Host | smart-eab4b673-c53f-4d83-bb7f-cb602f9d7ef2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231948988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1231948988 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_burst_write/latest |
Test location | /workspace/coverage/default/40.kmac_entropy_refresh.3923385573 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 7840776289 ps |
CPU time | 63.21 seconds |
Started | Jul 13 05:21:17 PM PDT 24 |
Finished | Jul 13 05:22:22 PM PDT 24 |
Peak memory | 229084 kb |
Host | smart-034712d3-7fd8-4111-b327-5b267b9e2e1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923385573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3923385573 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/40.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/40.kmac_key_error.3918613100 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 3933861683 ps |
CPU time | 10.09 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:21:37 PM PDT 24 |
Peak memory | 225100 kb |
Host | smart-0e80c8e4-c315-4df1-8b30-372e3a3b94d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918613100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3918613100 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_key_error/latest |
Test location | /workspace/coverage/default/40.kmac_lc_escalation.2891045416 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 3367493876 ps |
CPU time | 22.94 seconds |
Started | Jul 13 05:21:27 PM PDT 24 |
Finished | Jul 13 05:21:50 PM PDT 24 |
Peak memory | 234976 kb |
Host | smart-d758e9ac-fc25-42c8-a081-dcbb27ea0f6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891045416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2891045416 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/40.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/40.kmac_long_msg_and_output.41659639 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 19600003732 ps |
CPU time | 1846.03 seconds |
Started | Jul 13 05:21:05 PM PDT 24 |
Finished | Jul 13 05:51:52 PM PDT 24 |
Peak memory | 400000 kb |
Host | smart-67afecda-e760-45bc-9b76-826153cc99f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41659639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and _output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and _output.41659639 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/40.kmac_sideload.828185430 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 3740657077 ps |
CPU time | 305.96 seconds |
Started | Jul 13 05:21:07 PM PDT 24 |
Finished | Jul 13 05:26:14 PM PDT 24 |
Peak memory | 246580 kb |
Host | smart-a43639f2-edd3-43a9-8506-a6eca2f8f2d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828185430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.828185430 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_sideload/latest |
Test location | /workspace/coverage/default/40.kmac_smoke.1754838185 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 5137357789 ps |
CPU time | 55.21 seconds |
Started | Jul 13 05:21:06 PM PDT 24 |
Finished | Jul 13 05:22:01 PM PDT 24 |
Peak memory | 222532 kb |
Host | smart-dc0420e9-55e5-49cf-917d-e81dfaf58ccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754838185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1754838185 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_smoke/latest |
Test location | /workspace/coverage/default/40.kmac_stress_all.1362142012 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 7745859468 ps |
CPU time | 61.92 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:22:28 PM PDT 24 |
Peak memory | 239440 kb |
Host | smart-88b60d32-d2f7-459c-bee1-920f73467165 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1362142012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1362142012 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_stress_all/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_kmac.4149700123 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 213877787 ps |
CPU time | 5.95 seconds |
Started | Jul 13 05:21:17 PM PDT 24 |
Finished | Jul 13 05:21:23 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-4dccae00-c18b-4a3f-90a9-b61fc9619a68 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149700123 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.4149700123 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.639769934 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 368531092 ps |
CPU time | 6.29 seconds |
Started | Jul 13 05:21:16 PM PDT 24 |
Finished | Jul 13 05:21:23 PM PDT 24 |
Peak memory | 218516 kb |
Host | smart-d0b642fa-28d6-4e21-8b15-7a77a416717a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639769934 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 40.kmac_test_vectors_kmac_xof.639769934 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2286722617 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 20540164831 ps |
CPU time | 2121.05 seconds |
Started | Jul 13 05:21:07 PM PDT 24 |
Finished | Jul 13 05:56:29 PM PDT 24 |
Peak memory | 399532 kb |
Host | smart-7d7fedda-3fd4-45e9-ad75-6278bbab994d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2286722617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2286722617 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_256.2307819269 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 967618260752 ps |
CPU time | 2355.33 seconds |
Started | Jul 13 05:21:17 PM PDT 24 |
Finished | Jul 13 06:00:34 PM PDT 24 |
Peak memory | 376108 kb |
Host | smart-f17fab7c-5996-43c5-8789-144ee27268a2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2307819269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2307819269 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_384.230933745 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 506310921357 ps |
CPU time | 1927.49 seconds |
Started | Jul 13 05:21:18 PM PDT 24 |
Finished | Jul 13 05:53:26 PM PDT 24 |
Peak memory | 341844 kb |
Host | smart-6ee98624-9775-4329-94d9-9c53bd117cef |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=230933745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.230933745 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1617416978 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 43697554807 ps |
CPU time | 1143.72 seconds |
Started | Jul 13 05:21:18 PM PDT 24 |
Finished | Jul 13 05:40:22 PM PDT 24 |
Peak memory | 297352 kb |
Host | smart-26537609-d656-41ef-b2cf-8c4a60fed45f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1617416978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1617416978 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_shake_128.405963300 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 130204076748 ps |
CPU time | 5056.23 seconds |
Started | Jul 13 05:21:18 PM PDT 24 |
Finished | Jul 13 06:45:35 PM PDT 24 |
Peak memory | 651484 kb |
Host | smart-99c7fbed-6004-41d2-9c33-721cdab29974 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=405963300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.405963300 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/40.kmac_test_vectors_shake_256.3324386774 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 105200391091 ps |
CPU time | 4503.03 seconds |
Started | Jul 13 05:21:17 PM PDT 24 |
Finished | Jul 13 06:36:21 PM PDT 24 |
Peak memory | 568296 kb |
Host | smart-4dfd8103-2017-416c-b85e-39ed39ee8a66 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3324386774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3324386774 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/40.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/41.kmac_alert_test.230086455 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 31549504 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:21:44 PM PDT 24 |
Finished | Jul 13 05:21:45 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-29ae43fc-771a-4b95-bb51-fd6958d49929 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230086455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.230086455 +enable_m asking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_alert_test/latest |
Test location | /workspace/coverage/default/41.kmac_app.2153436020 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 57483006984 ps |
CPU time | 195.51 seconds |
Started | Jul 13 05:21:36 PM PDT 24 |
Finished | Jul 13 05:24:52 PM PDT 24 |
Peak memory | 239868 kb |
Host | smart-f69c128c-f3f1-4bdf-b6b3-3502148676db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153436020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2153436020 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_app/latest |
Test location | /workspace/coverage/default/41.kmac_burst_write.3258851020 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 55507911142 ps |
CPU time | 1142.05 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:40:29 PM PDT 24 |
Peak memory | 236612 kb |
Host | smart-dca566aa-187e-4b74-92ad-21f8b1e0ce7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258851020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3258851020 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_burst_write/latest |
Test location | /workspace/coverage/default/41.kmac_entropy_refresh.1316686982 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 93595879599 ps |
CPU time | 286.27 seconds |
Started | Jul 13 05:21:36 PM PDT 24 |
Finished | Jul 13 05:26:23 PM PDT 24 |
Peak memory | 245448 kb |
Host | smart-e2c1f71e-6ee8-43b2-9729-a386cefeb60e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316686982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1316686982 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/41.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/41.kmac_error.4104922035 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 11011385747 ps |
CPU time | 410.57 seconds |
Started | Jul 13 05:21:34 PM PDT 24 |
Finished | Jul 13 05:28:26 PM PDT 24 |
Peak memory | 271196 kb |
Host | smart-80f388be-2d60-4f8b-ac59-3638bfce72b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104922035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.4104922035 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_error/latest |
Test location | /workspace/coverage/default/41.kmac_key_error.809136037 |
Short name | T1066 |
Test name | |
Test status | |
Simulation time | 910431814 ps |
CPU time | 7.8 seconds |
Started | Jul 13 05:21:34 PM PDT 24 |
Finished | Jul 13 05:21:42 PM PDT 24 |
Peak memory | 222848 kb |
Host | smart-a8cea524-fbad-426c-85b8-6527a8b298cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809136037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.809136037 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_key_error/latest |
Test location | /workspace/coverage/default/41.kmac_lc_escalation.3101573684 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 15391942667 ps |
CPU time | 21.04 seconds |
Started | Jul 13 05:21:33 PM PDT 24 |
Finished | Jul 13 05:21:55 PM PDT 24 |
Peak memory | 235000 kb |
Host | smart-4b2573a9-aa8b-4671-bfc5-43c2a54b4428 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101573684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3101573684 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/41.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/41.kmac_long_msg_and_output.2887434760 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 319797510689 ps |
CPU time | 2126.11 seconds |
Started | Jul 13 05:21:27 PM PDT 24 |
Finished | Jul 13 05:56:54 PM PDT 24 |
Peak memory | 383524 kb |
Host | smart-8699d5fc-892e-46a9-a96a-0ece2f579e98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887434760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.2887434760 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/41.kmac_sideload.3338497172 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 12218297812 ps |
CPU time | 387.59 seconds |
Started | Jul 13 05:21:28 PM PDT 24 |
Finished | Jul 13 05:27:56 PM PDT 24 |
Peak memory | 251472 kb |
Host | smart-de7da403-254a-4a5b-aa62-68c53cb7efb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338497172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3338497172 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_sideload/latest |
Test location | /workspace/coverage/default/41.kmac_smoke.4078247871 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 7324064058 ps |
CPU time | 34.52 seconds |
Started | Jul 13 05:21:29 PM PDT 24 |
Finished | Jul 13 05:22:03 PM PDT 24 |
Peak memory | 222768 kb |
Host | smart-9640778a-4165-48aa-ad7f-cf5deaed62bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078247871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4078247871 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_smoke/latest |
Test location | /workspace/coverage/default/41.kmac_stress_all.3432918610 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 2229457175 ps |
CPU time | 48.39 seconds |
Started | Jul 13 05:21:44 PM PDT 24 |
Finished | Jul 13 05:22:32 PM PDT 24 |
Peak memory | 225868 kb |
Host | smart-1cf69c68-afc8-4e47-9f3b-0ca5d61b22ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3432918610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3432918610 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_stress_all/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_kmac.4174945607 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 97409282 ps |
CPU time | 5.63 seconds |
Started | Jul 13 05:21:36 PM PDT 24 |
Finished | Jul 13 05:21:42 PM PDT 24 |
Peak memory | 218540 kb |
Host | smart-82229902-a4aa-4138-a191-fea559eb149a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174945607 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.4174945607 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2475698768 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 1042926837 ps |
CPU time | 6.38 seconds |
Started | Jul 13 05:21:35 PM PDT 24 |
Finished | Jul 13 05:21:42 PM PDT 24 |
Peak memory | 218436 kb |
Host | smart-2de398ca-b583-4e44-a5fe-2f3b83600a36 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475698768 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2475698768 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_224.854149918 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 25821689657 ps |
CPU time | 2075.45 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:56:03 PM PDT 24 |
Peak memory | 398416 kb |
Host | smart-9abcd97f-99c8-44e0-b96a-02b9227d375d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=854149918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.854149918 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1729122570 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 163091284301 ps |
CPU time | 2065.77 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:55:52 PM PDT 24 |
Peak memory | 386052 kb |
Host | smart-832a6fb5-569b-4a38-ae0a-12f154964623 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1729122570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1729122570 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_384.3409327505 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 198613575400 ps |
CPU time | 1693.81 seconds |
Started | Jul 13 05:21:26 PM PDT 24 |
Finished | Jul 13 05:49:40 PM PDT 24 |
Peak memory | 341380 kb |
Host | smart-f8604f32-67a9-4550-9fb3-1ed2fee0a113 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3409327505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.3409327505 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_512.177298147 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 199360791968 ps |
CPU time | 1305.42 seconds |
Started | Jul 13 05:21:35 PM PDT 24 |
Finished | Jul 13 05:43:21 PM PDT 24 |
Peak memory | 294324 kb |
Host | smart-4aae8144-6a45-4624-8455-03094a25a51c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=177298147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.177298147 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_shake_128.3760909086 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 209546095031 ps |
CPU time | 5725.18 seconds |
Started | Jul 13 05:21:34 PM PDT 24 |
Finished | Jul 13 06:57:00 PM PDT 24 |
Peak memory | 659396 kb |
Host | smart-f56bf531-db07-42a7-9808-26ff6ef3bb8c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3760909086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3760909086 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/41.kmac_test_vectors_shake_256.732696927 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 64437861104 ps |
CPU time | 4304.8 seconds |
Started | Jul 13 05:21:37 PM PDT 24 |
Finished | Jul 13 06:33:22 PM PDT 24 |
Peak memory | 574460 kb |
Host | smart-e415e48f-2af0-4d2f-b879-dcb894989eee |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=732696927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.732696927 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/41.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/42.kmac_alert_test.3352021377 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 39330041 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:22:10 PM PDT 24 |
Finished | Jul 13 05:22:11 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-840a10bd-edb7-402c-b98c-5406d649a5b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352021377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3352021377 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_alert_test/latest |
Test location | /workspace/coverage/default/42.kmac_app.2856098227 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 16241996847 ps |
CPU time | 197.46 seconds |
Started | Jul 13 05:22:03 PM PDT 24 |
Finished | Jul 13 05:25:21 PM PDT 24 |
Peak memory | 240064 kb |
Host | smart-8bda0850-a388-40dd-b5b2-24ff8d840b8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856098227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2856098227 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_app/latest |
Test location | /workspace/coverage/default/42.kmac_burst_write.856366842 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 56074302085 ps |
CPU time | 1275.32 seconds |
Started | Jul 13 05:21:55 PM PDT 24 |
Finished | Jul 13 05:43:10 PM PDT 24 |
Peak memory | 238640 kb |
Host | smart-f35201c6-6fbc-4568-b323-7e8f6886cbf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856366842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.856366842 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_burst_write/latest |
Test location | /workspace/coverage/default/42.kmac_entropy_refresh.2769319698 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 2621156073 ps |
CPU time | 58.07 seconds |
Started | Jul 13 05:22:02 PM PDT 24 |
Finished | Jul 13 05:23:00 PM PDT 24 |
Peak memory | 229116 kb |
Host | smart-39ff16c7-0322-48dd-bf49-dad1737c4f57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769319698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2769319698 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/42.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/42.kmac_error.4155556976 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 13502917764 ps |
CPU time | 217.17 seconds |
Started | Jul 13 05:22:03 PM PDT 24 |
Finished | Jul 13 05:25:40 PM PDT 24 |
Peak memory | 252136 kb |
Host | smart-4d74bab3-60b8-405c-a54a-d110296ac285 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155556976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.4155556976 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_error/latest |
Test location | /workspace/coverage/default/42.kmac_key_error.745034400 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 762794259 ps |
CPU time | 3.15 seconds |
Started | Jul 13 05:22:00 PM PDT 24 |
Finished | Jul 13 05:22:04 PM PDT 24 |
Peak memory | 222628 kb |
Host | smart-223f2985-3973-4287-bebd-0571a2bf841f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745034400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.745034400 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_key_error/latest |
Test location | /workspace/coverage/default/42.kmac_lc_escalation.946371216 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 116588785 ps |
CPU time | 1.32 seconds |
Started | Jul 13 05:22:00 PM PDT 24 |
Finished | Jul 13 05:22:01 PM PDT 24 |
Peak memory | 226508 kb |
Host | smart-7ba793d7-8c57-4125-9e04-45f9fd187ce1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946371216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.946371216 +enable_masking=1 +sw_key _masked=0 |
Directory | /workspace/42.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/42.kmac_long_msg_and_output.3885625908 |
Short name | T1072 |
Test name | |
Test status | |
Simulation time | 269295477519 ps |
CPU time | 2509.96 seconds |
Started | Jul 13 05:21:44 PM PDT 24 |
Finished | Jul 13 06:03:34 PM PDT 24 |
Peak memory | 419700 kb |
Host | smart-93cb7a68-c10e-436d-a6d8-2bffce96609f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885625908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.3885625908 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/42.kmac_sideload.244801564 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 5474815225 ps |
CPU time | 426.03 seconds |
Started | Jul 13 05:21:54 PM PDT 24 |
Finished | Jul 13 05:29:00 PM PDT 24 |
Peak memory | 251620 kb |
Host | smart-da37bd80-599d-462d-bbf0-97f7813bd53d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244801564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.244801564 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_sideload/latest |
Test location | /workspace/coverage/default/42.kmac_smoke.3023361256 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 7789522327 ps |
CPU time | 76.91 seconds |
Started | Jul 13 05:21:43 PM PDT 24 |
Finished | Jul 13 05:23:00 PM PDT 24 |
Peak memory | 226636 kb |
Host | smart-0629a33d-2c34-4340-aaa5-c55c03bc7b24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023361256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3023361256 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_smoke/latest |
Test location | /workspace/coverage/default/42.kmac_stress_all.1778566399 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 193007416237 ps |
CPU time | 1546.22 seconds |
Started | Jul 13 05:22:02 PM PDT 24 |
Finished | Jul 13 05:47:48 PM PDT 24 |
Peak memory | 380728 kb |
Host | smart-e190d61d-6f98-4d54-9370-b01ed977dda3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1778566399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1778566399 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_stress_all/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_kmac.2693138357 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 370480008 ps |
CPU time | 5.45 seconds |
Started | Jul 13 05:22:01 PM PDT 24 |
Finished | Jul 13 05:22:07 PM PDT 24 |
Peak memory | 219484 kb |
Host | smart-aa9727dd-16b7-413a-8740-876b06026fb9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693138357 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.kmac_test_vectors_kmac.2693138357 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2572712574 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 415486324 ps |
CPU time | 6.48 seconds |
Started | Jul 13 05:22:01 PM PDT 24 |
Finished | Jul 13 05:22:08 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-39ac07d5-27e8-4f20-82e2-41f1de2a5b5c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572712574 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2572712574 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_224.731499434 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 132099153421 ps |
CPU time | 2135.9 seconds |
Started | Jul 13 05:21:52 PM PDT 24 |
Finished | Jul 13 05:57:29 PM PDT 24 |
Peak memory | 393100 kb |
Host | smart-0ac6db70-d722-4781-80ed-3b426148aba3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=731499434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.731499434 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3440235559 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 19993147465 ps |
CPU time | 1890.5 seconds |
Started | Jul 13 05:21:53 PM PDT 24 |
Finished | Jul 13 05:53:24 PM PDT 24 |
Peak memory | 382480 kb |
Host | smart-6152f2e3-59f3-4840-80fb-211612085854 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3440235559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3440235559 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_384.6982731 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 278231774660 ps |
CPU time | 1786.66 seconds |
Started | Jul 13 05:22:01 PM PDT 24 |
Finished | Jul 13 05:51:48 PM PDT 24 |
Peak memory | 336488 kb |
Host | smart-3662ff93-d8b2-4d87-8f2e-a596e4d13083 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=6982731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.6982731 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3066257082 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 43087875708 ps |
CPU time | 1112.03 seconds |
Started | Jul 13 05:22:00 PM PDT 24 |
Finished | Jul 13 05:40:33 PM PDT 24 |
Peak memory | 298516 kb |
Host | smart-a1dc3820-bf3d-4713-b198-6c5289550f24 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3066257082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3066257082 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_shake_128.3296734098 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 442416714466 ps |
CPU time | 5294.01 seconds |
Started | Jul 13 05:22:02 PM PDT 24 |
Finished | Jul 13 06:50:17 PM PDT 24 |
Peak memory | 653908 kb |
Host | smart-01db884a-8889-4c54-ae53-f33dec23c113 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3296734098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3296734098 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/42.kmac_test_vectors_shake_256.148334187 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 2172529496343 ps |
CPU time | 5682.26 seconds |
Started | Jul 13 05:22:01 PM PDT 24 |
Finished | Jul 13 06:56:44 PM PDT 24 |
Peak memory | 583464 kb |
Host | smart-039e6601-6fbc-4a9a-a874-0907cd028f59 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=148334187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.148334187 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/42.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/43.kmac_alert_test.93030974 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 13140600 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:22:38 PM PDT 24 |
Finished | Jul 13 05:22:39 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-469bcd1b-9c8d-4d46-ae37-f5b3a157d78d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93030974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.93030974 +enable_mas king=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_alert_test/latest |
Test location | /workspace/coverage/default/43.kmac_app.3199196480 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 5295381441 ps |
CPU time | 146.68 seconds |
Started | Jul 13 05:22:19 PM PDT 24 |
Finished | Jul 13 05:24:46 PM PDT 24 |
Peak memory | 237736 kb |
Host | smart-d294c62f-8759-4ab2-82d0-39382d503ba2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199196480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3199196480 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_app/latest |
Test location | /workspace/coverage/default/43.kmac_burst_write.2537520387 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 28883767781 ps |
CPU time | 815.96 seconds |
Started | Jul 13 05:22:10 PM PDT 24 |
Finished | Jul 13 05:35:47 PM PDT 24 |
Peak memory | 234556 kb |
Host | smart-aeb10bbd-caaa-4af6-b1e7-cbbc0f4a27b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537520387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.2537520387 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_burst_write/latest |
Test location | /workspace/coverage/default/43.kmac_entropy_refresh.1291889844 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 46307229860 ps |
CPU time | 240.78 seconds |
Started | Jul 13 05:22:28 PM PDT 24 |
Finished | Jul 13 05:26:29 PM PDT 24 |
Peak memory | 242548 kb |
Host | smart-3842d878-ba7a-4d9e-a669-a54557f5543e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291889844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1291889844 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/43.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/43.kmac_key_error.2851832562 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 5136510891 ps |
CPU time | 9.73 seconds |
Started | Jul 13 05:22:29 PM PDT 24 |
Finished | Jul 13 05:22:39 PM PDT 24 |
Peak memory | 225084 kb |
Host | smart-cc179619-603f-488e-9c32-f3a3dd7c325a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851832562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2851832562 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_key_error/latest |
Test location | /workspace/coverage/default/43.kmac_lc_escalation.4201195891 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 117716273 ps |
CPU time | 1.38 seconds |
Started | Jul 13 05:22:29 PM PDT 24 |
Finished | Jul 13 05:22:31 PM PDT 24 |
Peak memory | 226608 kb |
Host | smart-c8165b76-968c-460e-8d89-4ed77dc23167 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201195891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.4201195891 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/43.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/43.kmac_long_msg_and_output.1369593152 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 128232670051 ps |
CPU time | 3348.99 seconds |
Started | Jul 13 05:22:11 PM PDT 24 |
Finished | Jul 13 06:18:00 PM PDT 24 |
Peak memory | 471684 kb |
Host | smart-95c12b18-b306-43ae-a332-505ec0096c6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369593152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.1369593152 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/43.kmac_sideload.380362864 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 10333118202 ps |
CPU time | 392.24 seconds |
Started | Jul 13 05:22:10 PM PDT 24 |
Finished | Jul 13 05:28:43 PM PDT 24 |
Peak memory | 251456 kb |
Host | smart-fa0ef6ea-170d-4ad2-8d68-a46d49afe524 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380362864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.380362864 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_sideload/latest |
Test location | /workspace/coverage/default/43.kmac_smoke.3334566426 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 14308732514 ps |
CPU time | 28.13 seconds |
Started | Jul 13 05:22:10 PM PDT 24 |
Finished | Jul 13 05:22:38 PM PDT 24 |
Peak memory | 226556 kb |
Host | smart-987fffc3-1c58-4713-8c87-5e7bbf487905 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334566426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3334566426 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_smoke/latest |
Test location | /workspace/coverage/default/43.kmac_stress_all.1771197385 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 35092280653 ps |
CPU time | 1189.52 seconds |
Started | Jul 13 05:22:29 PM PDT 24 |
Finished | Jul 13 05:42:19 PM PDT 24 |
Peak memory | 325924 kb |
Host | smart-56eeeac5-b4ff-471b-8edb-c95d034b7e4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1771197385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1771197385 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_stress_all/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_kmac.1084876469 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 105026097 ps |
CPU time | 5.5 seconds |
Started | Jul 13 05:22:21 PM PDT 24 |
Finished | Jul 13 05:22:26 PM PDT 24 |
Peak memory | 218404 kb |
Host | smart-73d5fed7-938f-4c4d-a18e-d06e82cd1e91 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084876469 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.1084876469 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1096272448 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 186441548 ps |
CPU time | 5.8 seconds |
Started | Jul 13 05:22:21 PM PDT 24 |
Finished | Jul 13 05:22:27 PM PDT 24 |
Peak memory | 219768 kb |
Host | smart-e1854863-9a68-487e-9961-1053c05523f9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096272448 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1096272448 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3832466328 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 45549831437 ps |
CPU time | 2032.83 seconds |
Started | Jul 13 05:22:11 PM PDT 24 |
Finished | Jul 13 05:56:04 PM PDT 24 |
Peak memory | 395728 kb |
Host | smart-f2d75479-ad88-4479-a3b8-397cb85c8b3b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3832466328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3832466328 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_256.2987397744 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 65136182685 ps |
CPU time | 2094.69 seconds |
Started | Jul 13 05:22:10 PM PDT 24 |
Finished | Jul 13 05:57:06 PM PDT 24 |
Peak memory | 389376 kb |
Host | smart-b7976245-2fa0-4e4b-91eb-e152bc50f929 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2987397744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2987397744 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_384.775292720 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 14742022835 ps |
CPU time | 1503.27 seconds |
Started | Jul 13 05:22:19 PM PDT 24 |
Finished | Jul 13 05:47:23 PM PDT 24 |
Peak memory | 333432 kb |
Host | smart-81a7cfd5-ed2b-4ec7-9af0-231eb2f84d18 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=775292720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.775292720 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_512.3200987068 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 35347664833 ps |
CPU time | 1321.79 seconds |
Started | Jul 13 05:22:19 PM PDT 24 |
Finished | Jul 13 05:44:21 PM PDT 24 |
Peak memory | 303140 kb |
Host | smart-c635541c-e34a-4479-8e29-5d962bb6e96a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3200987068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3200987068 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_shake_128.1699111413 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 348078684292 ps |
CPU time | 5225.38 seconds |
Started | Jul 13 05:22:18 PM PDT 24 |
Finished | Jul 13 06:49:25 PM PDT 24 |
Peak memory | 654244 kb |
Host | smart-8101e835-cd15-4960-b9b2-9ad03beb6ffa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1699111413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1699111413 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/43.kmac_test_vectors_shake_256.3862695860 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 62382973595 ps |
CPU time | 4198.68 seconds |
Started | Jul 13 05:22:19 PM PDT 24 |
Finished | Jul 13 06:32:18 PM PDT 24 |
Peak memory | 565228 kb |
Host | smart-e02e3db0-4bd1-4522-a810-be5c8d251f0c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3862695860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3862695860 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/43.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/44.kmac_alert_test.2603744433 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 20817267 ps |
CPU time | 0.8 seconds |
Started | Jul 13 05:22:55 PM PDT 24 |
Finished | Jul 13 05:22:56 PM PDT 24 |
Peak memory | 218184 kb |
Host | smart-206dad0a-02aa-4c73-bbfe-8838a1ae48ad |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603744433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2603744433 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_alert_test/latest |
Test location | /workspace/coverage/default/44.kmac_app.1747283007 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 3936672105 ps |
CPU time | 241.13 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:26:48 PM PDT 24 |
Peak memory | 244648 kb |
Host | smart-15e89613-a3b4-474e-8f94-9f8b22033cc9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747283007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1747283007 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_app/latest |
Test location | /workspace/coverage/default/44.kmac_burst_write.780489608 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 4999035415 ps |
CPU time | 260.52 seconds |
Started | Jul 13 05:22:38 PM PDT 24 |
Finished | Jul 13 05:26:59 PM PDT 24 |
Peak memory | 229676 kb |
Host | smart-206cfb47-4098-4c51-824b-e7ddc88266a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780489608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.780489608 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_burst_write/latest |
Test location | /workspace/coverage/default/44.kmac_entropy_refresh.274487241 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 24635831300 ps |
CPU time | 159.99 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:25:27 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-b4e43b84-7bac-4248-b544-a925f7394596 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274487241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.274487241 +enable_masking=1 +sw _key_masked=0 |
Directory | /workspace/44.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/44.kmac_error.2137963027 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 5381092849 ps |
CPU time | 145.52 seconds |
Started | Jul 13 05:22:47 PM PDT 24 |
Finished | Jul 13 05:25:13 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-36368b7a-2416-48f9-bbe7-771a706952ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137963027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2137963027 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_error/latest |
Test location | /workspace/coverage/default/44.kmac_key_error.27719299 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 995028699 ps |
CPU time | 4.94 seconds |
Started | Jul 13 05:22:47 PM PDT 24 |
Finished | Jul 13 05:22:53 PM PDT 24 |
Peak memory | 223220 kb |
Host | smart-6a0f2020-da59-423c-91f7-f41638e2660a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27719299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.27719299 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_key_error/latest |
Test location | /workspace/coverage/default/44.kmac_long_msg_and_output.1862009630 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 7090760826 ps |
CPU time | 702.47 seconds |
Started | Jul 13 05:22:37 PM PDT 24 |
Finished | Jul 13 05:34:20 PM PDT 24 |
Peak memory | 290252 kb |
Host | smart-54286929-96da-494c-b8ce-80f20676deaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862009630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.1862009630 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/44.kmac_sideload.67330247 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 3872210194 ps |
CPU time | 19.6 seconds |
Started | Jul 13 05:22:37 PM PDT 24 |
Finished | Jul 13 05:22:56 PM PDT 24 |
Peak memory | 226688 kb |
Host | smart-987b91c4-c62a-4e66-848c-cd6e3d85d2c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67330247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.67330247 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_sideload/latest |
Test location | /workspace/coverage/default/44.kmac_smoke.3317128813 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 5168304298 ps |
CPU time | 50.19 seconds |
Started | Jul 13 05:22:37 PM PDT 24 |
Finished | Jul 13 05:23:27 PM PDT 24 |
Peak memory | 223208 kb |
Host | smart-0c3da2c2-2588-4675-8bfb-5d75dd49e229 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317128813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3317128813 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_smoke/latest |
Test location | /workspace/coverage/default/44.kmac_stress_all.1273999145 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 43626566372 ps |
CPU time | 618.09 seconds |
Started | Jul 13 05:22:55 PM PDT 24 |
Finished | Jul 13 05:33:13 PM PDT 24 |
Peak memory | 325360 kb |
Host | smart-be0376a9-3da7-40f9-9796-76fa4aa33b40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1273999145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1273999145 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_stress_all/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_kmac.1211224518 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 983393948 ps |
CPU time | 6.89 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:22:53 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-f6df4d49-1e4e-43e9-baad-fcaab791d08a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211224518 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.kmac_test_vectors_kmac.1211224518 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2125868970 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 155895621 ps |
CPU time | 6.14 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:22:52 PM PDT 24 |
Peak memory | 218564 kb |
Host | smart-cca0e45e-40ee-4f91-a0fe-cf7c7decabaf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125868970 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2125868970 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_224.4247279118 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 72108286009 ps |
CPU time | 2192.13 seconds |
Started | Jul 13 05:22:37 PM PDT 24 |
Finished | Jul 13 05:59:10 PM PDT 24 |
Peak memory | 400644 kb |
Host | smart-897771e0-2455-444a-86cc-f698462c8fee |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4247279118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.4247279118 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_256.1395569458 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 115173758894 ps |
CPU time | 2067.29 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:57:14 PM PDT 24 |
Peak memory | 385732 kb |
Host | smart-59e1ee87-5be9-496c-8991-cf2e95b9032e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1395569458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.1395569458 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_384.1228978943 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 47085038149 ps |
CPU time | 1596.61 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:49:23 PM PDT 24 |
Peak memory | 338636 kb |
Host | smart-fe0b94d4-a839-46a0-827b-46bd5b3bcaf4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1228978943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.1228978943 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_512.312834866 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 12141205512 ps |
CPU time | 1123.2 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 05:41:30 PM PDT 24 |
Peak memory | 300888 kb |
Host | smart-c21733a3-7b17-43ef-9b9b-8b9a1e5cc3e8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=312834866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.312834866 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_shake_128.1785180881 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 2565336556381 ps |
CPU time | 5960.13 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 07:02:07 PM PDT 24 |
Peak memory | 650588 kb |
Host | smart-26b23c1f-6ba2-4c6c-a73d-5736eb38e08b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1785180881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1785180881 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/44.kmac_test_vectors_shake_256.806410925 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 889535554539 ps |
CPU time | 5036.8 seconds |
Started | Jul 13 05:22:46 PM PDT 24 |
Finished | Jul 13 06:46:44 PM PDT 24 |
Peak memory | 568772 kb |
Host | smart-c522f6c1-1e52-4330-876e-8fbabe3d55ed |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=806410925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.806410925 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/44.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/45.kmac_alert_test.2167417447 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 14384003 ps |
CPU time | 0.82 seconds |
Started | Jul 13 05:23:25 PM PDT 24 |
Finished | Jul 13 05:23:26 PM PDT 24 |
Peak memory | 218288 kb |
Host | smart-a609e26f-3b05-4883-b94b-09aa0d67efcf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167417447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2167417447 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_alert_test/latest |
Test location | /workspace/coverage/default/45.kmac_app.1391545262 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 34001672278 ps |
CPU time | 258.86 seconds |
Started | Jul 13 05:23:12 PM PDT 24 |
Finished | Jul 13 05:27:31 PM PDT 24 |
Peak memory | 244040 kb |
Host | smart-2f0b084c-9f38-422d-b63b-4ab52d53c745 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391545262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1391545262 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_app/latest |
Test location | /workspace/coverage/default/45.kmac_burst_write.1825322996 |
Short name | T1071 |
Test name | |
Test status | |
Simulation time | 8889386037 ps |
CPU time | 211.77 seconds |
Started | Jul 13 05:22:54 PM PDT 24 |
Finished | Jul 13 05:26:26 PM PDT 24 |
Peak memory | 236764 kb |
Host | smart-5224a281-b08d-4508-a05d-362bd3322b9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825322996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1825322996 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_burst_write/latest |
Test location | /workspace/coverage/default/45.kmac_entropy_refresh.3735562148 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 472828815 ps |
CPU time | 7.63 seconds |
Started | Jul 13 05:23:15 PM PDT 24 |
Finished | Jul 13 05:23:23 PM PDT 24 |
Peak memory | 226896 kb |
Host | smart-c0a65287-aa5d-4bae-8b82-1c76f9ddda69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735562148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3735562148 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/45.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/45.kmac_error.1723410437 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 11720093300 ps |
CPU time | 305.87 seconds |
Started | Jul 13 05:23:23 PM PDT 24 |
Finished | Jul 13 05:28:30 PM PDT 24 |
Peak memory | 259448 kb |
Host | smart-e12ff4d6-888f-4dbd-a2d4-769d612eee01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723410437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1723410437 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_error/latest |
Test location | /workspace/coverage/default/45.kmac_key_error.2409042042 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 328803435 ps |
CPU time | 2.95 seconds |
Started | Jul 13 05:23:26 PM PDT 24 |
Finished | Jul 13 05:23:29 PM PDT 24 |
Peak memory | 222300 kb |
Host | smart-aac54aba-49b8-4ef4-94a2-564886b8c17b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409042042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2409042042 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_key_error/latest |
Test location | /workspace/coverage/default/45.kmac_lc_escalation.1984001453 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 140838934 ps |
CPU time | 1.54 seconds |
Started | Jul 13 05:23:24 PM PDT 24 |
Finished | Jul 13 05:23:26 PM PDT 24 |
Peak memory | 226664 kb |
Host | smart-b5126ccb-ec26-4ad5-bd21-7b58472861f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984001453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1984001453 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/45.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/45.kmac_long_msg_and_output.2597179570 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 88869146094 ps |
CPU time | 3166.57 seconds |
Started | Jul 13 05:22:55 PM PDT 24 |
Finished | Jul 13 06:15:43 PM PDT 24 |
Peak memory | 480760 kb |
Host | smart-f8be85fa-34e6-4e7a-ac17-49bc28842490 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597179570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.2597179570 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/45.kmac_sideload.3012910991 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 7434819617 ps |
CPU time | 178.8 seconds |
Started | Jul 13 05:22:55 PM PDT 24 |
Finished | Jul 13 05:25:54 PM PDT 24 |
Peak memory | 238656 kb |
Host | smart-60a65c15-b58b-43c1-827d-594a6b7a5423 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012910991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3012910991 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_sideload/latest |
Test location | /workspace/coverage/default/45.kmac_smoke.3817472866 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 4041665655 ps |
CPU time | 33.99 seconds |
Started | Jul 13 05:22:55 PM PDT 24 |
Finished | Jul 13 05:23:29 PM PDT 24 |
Peak memory | 225276 kb |
Host | smart-5307904a-b950-4b7d-8833-bc8db0d396af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817472866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3817472866 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_smoke/latest |
Test location | /workspace/coverage/default/45.kmac_stress_all.3557180685 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 3361594874 ps |
CPU time | 196.4 seconds |
Started | Jul 13 05:23:24 PM PDT 24 |
Finished | Jul 13 05:26:41 PM PDT 24 |
Peak memory | 253500 kb |
Host | smart-28e57583-2e3f-4a3c-947a-8a017dc8d2b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3557180685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3557180685 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_stress_all/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_kmac.3577663874 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 565752925 ps |
CPU time | 6.85 seconds |
Started | Jul 13 05:23:12 PM PDT 24 |
Finished | Jul 13 05:23:19 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-b3ae56cd-bfba-479d-a72e-da1ed7f3894a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577663874 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.3577663874 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3604475910 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 300973093 ps |
CPU time | 6.33 seconds |
Started | Jul 13 05:23:11 PM PDT 24 |
Finished | Jul 13 05:23:18 PM PDT 24 |
Peak memory | 218404 kb |
Host | smart-a3a5fcf4-6f61-4c8a-9f79-278979a6c32c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604475910 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3604475910 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3618072282 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 100606242265 ps |
CPU time | 2477.69 seconds |
Started | Jul 13 05:23:02 PM PDT 24 |
Finished | Jul 13 06:04:20 PM PDT 24 |
Peak memory | 406524 kb |
Host | smart-a4f18338-1a76-404f-b55b-42c60c011823 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3618072282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3618072282 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3024372082 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 64125489482 ps |
CPU time | 2038.52 seconds |
Started | Jul 13 05:23:03 PM PDT 24 |
Finished | Jul 13 05:57:02 PM PDT 24 |
Peak memory | 388128 kb |
Host | smart-ea9d07a8-0a09-495e-a725-aa24d5d351b8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3024372082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3024372082 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2181193419 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 449191727034 ps |
CPU time | 1789.73 seconds |
Started | Jul 13 05:23:03 PM PDT 24 |
Finished | Jul 13 05:52:53 PM PDT 24 |
Peak memory | 345120 kb |
Host | smart-35811d0c-9266-462d-ad2d-95f4cf5f1ead |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2181193419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2181193419 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_512.2954766830 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 24594932376 ps |
CPU time | 1131.17 seconds |
Started | Jul 13 05:23:04 PM PDT 24 |
Finished | Jul 13 05:41:56 PM PDT 24 |
Peak memory | 300720 kb |
Host | smart-40644a64-e7c9-4428-923e-9c75d4519e1b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2954766830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.2954766830 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_shake_128.2885375990 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 126155292068 ps |
CPU time | 5283.69 seconds |
Started | Jul 13 05:23:13 PM PDT 24 |
Finished | Jul 13 06:51:17 PM PDT 24 |
Peak memory | 660972 kb |
Host | smart-5feebdeb-4b06-44ec-92ba-b939c7ef629c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2885375990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.2885375990 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/45.kmac_test_vectors_shake_256.1389073361 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 156269872225 ps |
CPU time | 5110.16 seconds |
Started | Jul 13 05:23:13 PM PDT 24 |
Finished | Jul 13 06:48:24 PM PDT 24 |
Peak memory | 578576 kb |
Host | smart-9012692c-509c-4ef9-a55a-7cc935f1ce41 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1389073361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.1389073361 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/45.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/46.kmac_alert_test.2712366182 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 14033063 ps |
CPU time | 0.95 seconds |
Started | Jul 13 05:23:44 PM PDT 24 |
Finished | Jul 13 05:23:45 PM PDT 24 |
Peak memory | 218184 kb |
Host | smart-e262bec0-138b-42dd-a42b-afb086d29808 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712366182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2712366182 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_alert_test/latest |
Test location | /workspace/coverage/default/46.kmac_app.231684496 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 9848421153 ps |
CPU time | 145.5 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 05:26:00 PM PDT 24 |
Peak memory | 236780 kb |
Host | smart-3395223b-061e-4a92-9dd8-954197fb6437 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231684496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.231684496 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_app/latest |
Test location | /workspace/coverage/default/46.kmac_burst_write.835717535 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 14856109479 ps |
CPU time | 1610.12 seconds |
Started | Jul 13 05:23:35 PM PDT 24 |
Finished | Jul 13 05:50:25 PM PDT 24 |
Peak memory | 243128 kb |
Host | smart-5e14806a-6f32-4799-95b3-e7785cd398fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835717535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.835717535 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_burst_write/latest |
Test location | /workspace/coverage/default/46.kmac_entropy_refresh.3060422647 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 3678282541 ps |
CPU time | 76.23 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 05:24:51 PM PDT 24 |
Peak memory | 228900 kb |
Host | smart-01e2fed9-113c-484c-8625-a4afacb3f0bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060422647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3060422647 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/46.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/46.kmac_error.59171655 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 3690300521 ps |
CPU time | 242.7 seconds |
Started | Jul 13 05:23:42 PM PDT 24 |
Finished | Jul 13 05:27:45 PM PDT 24 |
Peak memory | 251192 kb |
Host | smart-1a7571c9-9ab7-4a66-ab2b-d40773d23757 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59171655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.59171655 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_error/latest |
Test location | /workspace/coverage/default/46.kmac_key_error.2288432819 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 312906361 ps |
CPU time | 2.03 seconds |
Started | Jul 13 05:23:43 PM PDT 24 |
Finished | Jul 13 05:23:45 PM PDT 24 |
Peak memory | 222416 kb |
Host | smart-82dad53f-269e-4e04-9dca-c3b420b5ea5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288432819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2288432819 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_key_error/latest |
Test location | /workspace/coverage/default/46.kmac_lc_escalation.2524758216 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 74637723 ps |
CPU time | 1.42 seconds |
Started | Jul 13 05:23:43 PM PDT 24 |
Finished | Jul 13 05:23:45 PM PDT 24 |
Peak memory | 226540 kb |
Host | smart-5e9981e5-607e-4b13-aea2-fd654e86dbb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524758216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2524758216 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/46.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/46.kmac_long_msg_and_output.3106432754 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 86700875490 ps |
CPU time | 724.41 seconds |
Started | Jul 13 05:23:23 PM PDT 24 |
Finished | Jul 13 05:35:27 PM PDT 24 |
Peak memory | 280776 kb |
Host | smart-0a808396-c1cc-4489-9aff-28a1be2d4aee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106432754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.3106432754 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/46.kmac_sideload.3627657312 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 13937091198 ps |
CPU time | 259.61 seconds |
Started | Jul 13 05:23:24 PM PDT 24 |
Finished | Jul 13 05:27:44 PM PDT 24 |
Peak memory | 243964 kb |
Host | smart-9bdcfbc9-f06c-48f9-984b-00ac13d3586a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627657312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3627657312 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_sideload/latest |
Test location | /workspace/coverage/default/46.kmac_smoke.1606938470 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 1987459484 ps |
CPU time | 38.01 seconds |
Started | Jul 13 05:23:25 PM PDT 24 |
Finished | Jul 13 05:24:03 PM PDT 24 |
Peak memory | 226464 kb |
Host | smart-1b6299a4-2861-4e51-9452-e8f5c0a9aed8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606938470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1606938470 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_smoke/latest |
Test location | /workspace/coverage/default/46.kmac_stress_all.1876408882 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 108289961991 ps |
CPU time | 2712.67 seconds |
Started | Jul 13 05:23:41 PM PDT 24 |
Finished | Jul 13 06:08:54 PM PDT 24 |
Peak memory | 480152 kb |
Host | smart-16439ca9-5635-48cc-915f-1d6381984d09 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1876408882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1876408882 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_stress_all/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_kmac.3150574199 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 462865749 ps |
CPU time | 5.87 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 05:23:40 PM PDT 24 |
Peak memory | 218444 kb |
Host | smart-621b3599-8f34-48f6-a2ee-5428bf144e1c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150574199 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.3150574199 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1864293452 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 235496111 ps |
CPU time | 6.14 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 05:23:40 PM PDT 24 |
Peak memory | 219504 kb |
Host | smart-d2e66251-4d8a-4056-aca5-1166c593983f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864293452 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1864293452 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_224.3206939854 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 193132481238 ps |
CPU time | 2339.15 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 06:02:34 PM PDT 24 |
Peak memory | 395712 kb |
Host | smart-6d671856-8675-4f6f-b2c6-c811d2c130fa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3206939854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3206939854 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_256.62724031 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 933023161986 ps |
CPU time | 2577.69 seconds |
Started | Jul 13 05:23:35 PM PDT 24 |
Finished | Jul 13 06:06:33 PM PDT 24 |
Peak memory | 392452 kb |
Host | smart-cdd3ce0f-62ec-4c73-a035-f8ea0c947c05 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=62724031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.62724031 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2247268942 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 15247844075 ps |
CPU time | 1495.79 seconds |
Started | Jul 13 05:23:32 PM PDT 24 |
Finished | Jul 13 05:48:29 PM PDT 24 |
Peak memory | 342196 kb |
Host | smart-4bd56262-34bf-442f-8d27-f6613b526c52 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2247268942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2247268942 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_512.150405422 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 144387598268 ps |
CPU time | 1308.73 seconds |
Started | Jul 13 05:23:33 PM PDT 24 |
Finished | Jul 13 05:45:22 PM PDT 24 |
Peak memory | 300276 kb |
Host | smart-83e86134-3889-4b32-9cd2-8668e32f6b0b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=150405422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.150405422 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_shake_128.1117657565 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 749006116229 ps |
CPU time | 5116.89 seconds |
Started | Jul 13 05:23:34 PM PDT 24 |
Finished | Jul 13 06:48:52 PM PDT 24 |
Peak memory | 664016 kb |
Host | smart-7f4f0aad-bf79-45cd-a586-779a8e24b674 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1117657565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1117657565 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/46.kmac_test_vectors_shake_256.932183273 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 152440185336 ps |
CPU time | 4460.21 seconds |
Started | Jul 13 05:23:33 PM PDT 24 |
Finished | Jul 13 06:37:54 PM PDT 24 |
Peak memory | 565856 kb |
Host | smart-2d03f1cc-dbb6-4fd5-a46a-2b60252e8643 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=932183273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.932183273 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/46.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/47.kmac_alert_test.4115440721 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 54594160 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 05:24:10 PM PDT 24 |
Peak memory | 218188 kb |
Host | smart-0c66a557-6979-4c0b-b450-cf0d01f7ad9c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115440721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.4115440721 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_alert_test/latest |
Test location | /workspace/coverage/default/47.kmac_app.1049974856 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 3942345833 ps |
CPU time | 86.9 seconds |
Started | Jul 13 05:23:59 PM PDT 24 |
Finished | Jul 13 05:25:26 PM PDT 24 |
Peak memory | 231968 kb |
Host | smart-8a8916d7-68b2-4119-b773-5325d5d3ea83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049974856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1049974856 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_app/latest |
Test location | /workspace/coverage/default/47.kmac_burst_write.2490429703 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 110428902277 ps |
CPU time | 1379.16 seconds |
Started | Jul 13 05:23:50 PM PDT 24 |
Finished | Jul 13 05:46:50 PM PDT 24 |
Peak memory | 239776 kb |
Host | smart-799e88e1-fe70-4ec3-a812-146abc9eb155 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490429703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2490429703 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_burst_write/latest |
Test location | /workspace/coverage/default/47.kmac_entropy_refresh.2191218292 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 2853572670 ps |
CPU time | 49.78 seconds |
Started | Jul 13 05:24:00 PM PDT 24 |
Finished | Jul 13 05:24:51 PM PDT 24 |
Peak memory | 228456 kb |
Host | smart-c2e50056-c9a2-4313-81b9-3474f7fd872c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191218292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2191218292 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/47.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/47.kmac_error.1296533965 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 33269504200 ps |
CPU time | 179.75 seconds |
Started | Jul 13 05:23:57 PM PDT 24 |
Finished | Jul 13 05:26:57 PM PDT 24 |
Peak memory | 256420 kb |
Host | smart-350ba991-2b8c-47ba-8393-0c6f67abb3af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296533965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1296533965 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_error/latest |
Test location | /workspace/coverage/default/47.kmac_key_error.1762700942 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 919560713 ps |
CPU time | 7.77 seconds |
Started | Jul 13 05:24:00 PM PDT 24 |
Finished | Jul 13 05:24:08 PM PDT 24 |
Peak memory | 223576 kb |
Host | smart-2d68dc8c-1599-4068-89fc-e7d0ee9e1bbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762700942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1762700942 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_key_error/latest |
Test location | /workspace/coverage/default/47.kmac_lc_escalation.1776261991 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 42183101 ps |
CPU time | 1.42 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 05:24:10 PM PDT 24 |
Peak memory | 226504 kb |
Host | smart-8825b513-9c81-4cb1-aee9-c93553b97936 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776261991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1776261991 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/47.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/47.kmac_long_msg_and_output.3819210292 |
Short name | T1052 |
Test name | |
Test status | |
Simulation time | 38510890992 ps |
CPU time | 788.38 seconds |
Started | Jul 13 05:23:51 PM PDT 24 |
Finished | Jul 13 05:37:00 PM PDT 24 |
Peak memory | 293372 kb |
Host | smart-5f0f4012-d207-4560-a312-57708ad92053 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819210292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.3819210292 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/47.kmac_sideload.2120577320 |
Short name | T1044 |
Test name | |
Test status | |
Simulation time | 1309527274 ps |
CPU time | 103.33 seconds |
Started | Jul 13 05:23:52 PM PDT 24 |
Finished | Jul 13 05:25:36 PM PDT 24 |
Peak memory | 230936 kb |
Host | smart-1d5d2f45-a2b5-494d-9fed-ceb1cbc63570 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120577320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2120577320 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_sideload/latest |
Test location | /workspace/coverage/default/47.kmac_smoke.3854433129 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 2244136236 ps |
CPU time | 53.49 seconds |
Started | Jul 13 05:23:44 PM PDT 24 |
Finished | Jul 13 05:24:38 PM PDT 24 |
Peak memory | 218452 kb |
Host | smart-af1eb5fc-7802-4db3-ae3e-a03537b81977 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854433129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3854433129 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_smoke/latest |
Test location | /workspace/coverage/default/47.kmac_stress_all.667819334 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 109739150984 ps |
CPU time | 479.14 seconds |
Started | Jul 13 05:24:09 PM PDT 24 |
Finished | Jul 13 05:32:08 PM PDT 24 |
Peak memory | 268004 kb |
Host | smart-6285d8d0-93d7-4fc1-b24c-ed9d8bfdf90a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=667819334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.667819334 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_stress_all/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_kmac.1411831990 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 325074680 ps |
CPU time | 5.66 seconds |
Started | Jul 13 05:24:00 PM PDT 24 |
Finished | Jul 13 05:24:06 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-7fd56c56-9fcd-49b4-a4a6-4806cf430d56 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411831990 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.1411831990 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.1360944066 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 1431698812 ps |
CPU time | 6.18 seconds |
Started | Jul 13 05:24:00 PM PDT 24 |
Finished | Jul 13 05:24:06 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-189a8dd6-d52a-417a-86d6-051ca61638b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360944066 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.1360944066 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_224.4150955435 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 99715876962 ps |
CPU time | 2244.66 seconds |
Started | Jul 13 05:23:51 PM PDT 24 |
Finished | Jul 13 06:01:16 PM PDT 24 |
Peak memory | 389684 kb |
Host | smart-e68c091a-303e-40d9-8e2f-8a6af85a893c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4150955435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.4150955435 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2526624202 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 160245160148 ps |
CPU time | 2053.98 seconds |
Started | Jul 13 05:23:51 PM PDT 24 |
Finished | Jul 13 05:58:05 PM PDT 24 |
Peak memory | 388904 kb |
Host | smart-7ed823c0-094a-42f4-95ea-26b41141a157 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2526624202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2526624202 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_384.2542223580 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 60962733923 ps |
CPU time | 1551.99 seconds |
Started | Jul 13 05:23:52 PM PDT 24 |
Finished | Jul 13 05:49:44 PM PDT 24 |
Peak memory | 335532 kb |
Host | smart-b3dbda02-25b1-44d0-9711-d882576b6b98 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2542223580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2542223580 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1393099621 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 53928462363 ps |
CPU time | 1376.93 seconds |
Started | Jul 13 05:23:59 PM PDT 24 |
Finished | Jul 13 05:46:56 PM PDT 24 |
Peak memory | 301900 kb |
Host | smart-2a35a708-b42e-4528-a4e5-ee89bbf83b2e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1393099621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1393099621 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_shake_128.3665666992 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 1137213806552 ps |
CPU time | 6047 seconds |
Started | Jul 13 05:24:00 PM PDT 24 |
Finished | Jul 13 07:04:48 PM PDT 24 |
Peak memory | 664992 kb |
Host | smart-6104af23-db8d-4101-ae58-9e318b559302 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3665666992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3665666992 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/47.kmac_test_vectors_shake_256.3578746761 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 60515115600 ps |
CPU time | 4382.38 seconds |
Started | Jul 13 05:23:58 PM PDT 24 |
Finished | Jul 13 06:37:01 PM PDT 24 |
Peak memory | 571956 kb |
Host | smart-2ff082d2-5942-4c26-9bdb-f9ede0db771e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3578746761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3578746761 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/47.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/48.kmac_alert_test.3848797145 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 45832919 ps |
CPU time | 0.81 seconds |
Started | Jul 13 05:24:26 PM PDT 24 |
Finished | Jul 13 05:24:27 PM PDT 24 |
Peak memory | 218248 kb |
Host | smart-d847441f-623e-4aec-b3c0-6f6c2cb5494c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848797145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3848797145 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_alert_test/latest |
Test location | /workspace/coverage/default/48.kmac_app.2367061271 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 51316743901 ps |
CPU time | 346.18 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:30:14 PM PDT 24 |
Peak memory | 250396 kb |
Host | smart-44b2f5e7-87e6-45ff-a9d9-81adcc2b7abd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367061271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2367061271 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_app/latest |
Test location | /workspace/coverage/default/48.kmac_burst_write.4148615802 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 21660918415 ps |
CPU time | 943.3 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 05:39:52 PM PDT 24 |
Peak memory | 236672 kb |
Host | smart-7954dfe2-2cdf-4286-a216-b82026e891ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148615802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.4148615802 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_burst_write/latest |
Test location | /workspace/coverage/default/48.kmac_entropy_refresh.3782897789 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 84826141077 ps |
CPU time | 436.7 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:31:44 PM PDT 24 |
Peak memory | 252228 kb |
Host | smart-0703a421-abf7-4b29-92e2-68ba7df1dda6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782897789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3782897789 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/48.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/48.kmac_error.1102258272 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 2975702687 ps |
CPU time | 59.27 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:25:27 PM PDT 24 |
Peak memory | 243104 kb |
Host | smart-3fffbb66-fe8c-487e-8915-038437cf1793 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102258272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1102258272 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_error/latest |
Test location | /workspace/coverage/default/48.kmac_key_error.984303891 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 710373866 ps |
CPU time | 5.84 seconds |
Started | Jul 13 05:24:25 PM PDT 24 |
Finished | Jul 13 05:24:31 PM PDT 24 |
Peak memory | 223048 kb |
Host | smart-af50abb1-9b1e-4661-87a2-294496c754d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984303891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.984303891 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_key_error/latest |
Test location | /workspace/coverage/default/48.kmac_lc_escalation.2669795982 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 96667650 ps |
CPU time | 1.27 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:24:29 PM PDT 24 |
Peak memory | 226560 kb |
Host | smart-2def1d7a-2626-4697-b1ff-ff9c4303424a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669795982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2669795982 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/48.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/48.kmac_long_msg_and_output.2848751926 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 184616926057 ps |
CPU time | 2375.42 seconds |
Started | Jul 13 05:24:07 PM PDT 24 |
Finished | Jul 13 06:03:43 PM PDT 24 |
Peak memory | 406304 kb |
Host | smart-49627e11-edd1-4d68-bb31-6c7ec8761a4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848751926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.2848751926 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/48.kmac_sideload.1111348846 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 5842592414 ps |
CPU time | 54.71 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 05:25:03 PM PDT 24 |
Peak memory | 226888 kb |
Host | smart-c1ce2f01-23e4-488b-b50e-eb6546c2de1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111348846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1111348846 +e nable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_sideload/latest |
Test location | /workspace/coverage/default/48.kmac_smoke.611972674 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 8587043069 ps |
CPU time | 44.22 seconds |
Started | Jul 13 05:24:07 PM PDT 24 |
Finished | Jul 13 05:24:52 PM PDT 24 |
Peak memory | 222896 kb |
Host | smart-b57534de-b057-4497-8ed0-3cdf48e91cba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611972674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.611972674 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_smoke/latest |
Test location | /workspace/coverage/default/48.kmac_stress_all.1771074805 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 55410898705 ps |
CPU time | 798.58 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:37:46 PM PDT 24 |
Peak memory | 292996 kb |
Host | smart-2a100834-d927-474b-a651-5311a320f1f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1771074805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1771074805 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_stress_all/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_kmac.638826478 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 495786192 ps |
CPU time | 6.68 seconds |
Started | Jul 13 05:24:14 PM PDT 24 |
Finished | Jul 13 05:24:21 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-5e2ab87a-bebf-4cfa-b8ca-a06fccf165b7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638826478 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 48.kmac_test_vectors_kmac.638826478 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3989583143 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 98580520 ps |
CPU time | 5.91 seconds |
Started | Jul 13 05:24:27 PM PDT 24 |
Finished | Jul 13 05:24:33 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-fb7edad7-1060-4b49-a43c-4ce4a8630995 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989583143 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3989583143 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_224.391428355 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 49139706323 ps |
CPU time | 1909.11 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 05:55:58 PM PDT 24 |
Peak memory | 386996 kb |
Host | smart-f16f6b65-761c-4493-b758-a16ead32d50e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=391428355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.391428355 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_256.212659164 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 323830770230 ps |
CPU time | 2210.33 seconds |
Started | Jul 13 05:24:08 PM PDT 24 |
Finished | Jul 13 06:00:59 PM PDT 24 |
Peak memory | 391188 kb |
Host | smart-3d474f09-6f16-4375-a3af-3d75684b8ffc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=212659164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.212659164 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_384.2807357778 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 70622769164 ps |
CPU time | 1753.41 seconds |
Started | Jul 13 05:24:16 PM PDT 24 |
Finished | Jul 13 05:53:30 PM PDT 24 |
Peak memory | 337952 kb |
Host | smart-a64404bc-f93d-4509-9c85-f20e085493bd |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2807357778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.2807357778 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_512.322745592 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 614303319862 ps |
CPU time | 1546.26 seconds |
Started | Jul 13 05:24:18 PM PDT 24 |
Finished | Jul 13 05:50:05 PM PDT 24 |
Peak memory | 301612 kb |
Host | smart-e7960322-1cfa-4ba6-bbcf-c9678d381124 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=322745592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.322745592 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_shake_128.2317997170 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 2802812348901 ps |
CPU time | 5663.25 seconds |
Started | Jul 13 05:24:16 PM PDT 24 |
Finished | Jul 13 06:58:40 PM PDT 24 |
Peak memory | 645520 kb |
Host | smart-13505f5a-a85d-4724-b6d1-b1c0cd590835 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2317997170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2317997170 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/48.kmac_test_vectors_shake_256.1133261042 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 220758203941 ps |
CPU time | 4575.54 seconds |
Started | Jul 13 05:24:18 PM PDT 24 |
Finished | Jul 13 06:40:34 PM PDT 24 |
Peak memory | 569600 kb |
Host | smart-d5d0c572-1c9e-4f3b-975f-1ac2f1babd72 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1133261042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1133261042 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/48.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/49.kmac_alert_test.4152435116 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 132480765 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:25:11 PM PDT 24 |
Finished | Jul 13 05:25:13 PM PDT 24 |
Peak memory | 218236 kb |
Host | smart-63651fd8-ed22-4ad5-9811-6d4654615c4f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152435116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4152435116 +enable _masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_alert_test/latest |
Test location | /workspace/coverage/default/49.kmac_app.3451321295 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 4855543164 ps |
CPU time | 114.37 seconds |
Started | Jul 13 05:24:55 PM PDT 24 |
Finished | Jul 13 05:26:50 PM PDT 24 |
Peak memory | 235256 kb |
Host | smart-44e057b4-e6d0-4c09-beb8-89a30610e928 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451321295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3451321295 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_app/latest |
Test location | /workspace/coverage/default/49.kmac_burst_write.209533759 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 22847344380 ps |
CPU time | 1200.2 seconds |
Started | Jul 13 05:24:36 PM PDT 24 |
Finished | Jul 13 05:44:36 PM PDT 24 |
Peak memory | 242956 kb |
Host | smart-3d5cc4c3-6174-4d71-af11-46c0f5d4bcd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209533759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.209533759 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_burst_write/latest |
Test location | /workspace/coverage/default/49.kmac_entropy_refresh.2251791666 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 9047554434 ps |
CPU time | 190.37 seconds |
Started | Jul 13 05:24:55 PM PDT 24 |
Finished | Jul 13 05:28:06 PM PDT 24 |
Peak memory | 240420 kb |
Host | smart-0702e1be-48a9-46e5-a36f-88b519d0e8ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2251791666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2251791666 +enable_masking=1 + sw_key_masked=0 |
Directory | /workspace/49.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/49.kmac_error.703676719 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 38256734000 ps |
CPU time | 414.56 seconds |
Started | Jul 13 05:25:04 PM PDT 24 |
Finished | Jul 13 05:31:59 PM PDT 24 |
Peak memory | 266888 kb |
Host | smart-154d8fbb-dc98-4965-b9b2-21beb5923868 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703676719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.703676719 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_error/latest |
Test location | /workspace/coverage/default/49.kmac_key_error.1738813321 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 2683369550 ps |
CPU time | 9.74 seconds |
Started | Jul 13 05:25:04 PM PDT 24 |
Finished | Jul 13 05:25:14 PM PDT 24 |
Peak memory | 224872 kb |
Host | smart-6b7cd9fb-a88a-4fdd-ba3a-be763172f830 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738813321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1738813321 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_key_error/latest |
Test location | /workspace/coverage/default/49.kmac_lc_escalation.3987131138 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 97471236 ps |
CPU time | 1.34 seconds |
Started | Jul 13 05:25:04 PM PDT 24 |
Finished | Jul 13 05:25:06 PM PDT 24 |
Peak memory | 226512 kb |
Host | smart-82ca2b7d-d5e3-4f24-8d8e-0e1f10cf4b92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987131138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3987131138 +enable_masking=1 +sw_k ey_masked=0 |
Directory | /workspace/49.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/49.kmac_long_msg_and_output.2560344612 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 15893125789 ps |
CPU time | 1832 seconds |
Started | Jul 13 05:24:35 PM PDT 24 |
Finished | Jul 13 05:55:07 PM PDT 24 |
Peak memory | 379468 kb |
Host | smart-04aa71b2-adf9-4f76-8b6f-4d4337952d5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560344612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.2560344612 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/49.kmac_sideload.55433399 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 14515997237 ps |
CPU time | 447.88 seconds |
Started | Jul 13 05:24:36 PM PDT 24 |
Finished | Jul 13 05:32:05 PM PDT 24 |
Peak memory | 254776 kb |
Host | smart-a9853691-670f-494d-a6a1-bcb8020bebf2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55433399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.55433399 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_sideload/latest |
Test location | /workspace/coverage/default/49.kmac_smoke.2817527058 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 1408832302 ps |
CPU time | 31.3 seconds |
Started | Jul 13 05:24:36 PM PDT 24 |
Finished | Jul 13 05:25:08 PM PDT 24 |
Peak memory | 222828 kb |
Host | smart-bbb19988-ed8a-4f39-af8a-dc7f8c7debc2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817527058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2817527058 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_smoke/latest |
Test location | /workspace/coverage/default/49.kmac_stress_all.1536074916 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 57714040646 ps |
CPU time | 2150.37 seconds |
Started | Jul 13 05:25:12 PM PDT 24 |
Finished | Jul 13 06:01:03 PM PDT 24 |
Peak memory | 398696 kb |
Host | smart-9fb102ec-e3e2-4211-86ba-082b0545a507 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1536074916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1536074916 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_stress_all/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_kmac.3845423973 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 125102123 ps |
CPU time | 6.14 seconds |
Started | Jul 13 05:24:44 PM PDT 24 |
Finished | Jul 13 05:24:51 PM PDT 24 |
Peak memory | 218516 kb |
Host | smart-a6dc7101-e6bd-4717-8917-8f4333f77731 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845423973 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.3845423973 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3068156891 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 385463679 ps |
CPU time | 5.43 seconds |
Started | Jul 13 05:24:52 PM PDT 24 |
Finished | Jul 13 05:24:58 PM PDT 24 |
Peak memory | 218316 kb |
Host | smart-e3814fb0-8643-4090-bbda-7a491c3e1396 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068156891 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3068156891 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_224.31259767 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 19972313736 ps |
CPU time | 1884.14 seconds |
Started | Jul 13 05:24:36 PM PDT 24 |
Finished | Jul 13 05:56:00 PM PDT 24 |
Peak memory | 382436 kb |
Host | smart-1252477c-b5e0-4e92-acf9-b6f53fe54221 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=31259767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.31259767 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_256.2829767164 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 128480173066 ps |
CPU time | 2185.51 seconds |
Started | Jul 13 05:24:50 PM PDT 24 |
Finished | Jul 13 06:01:16 PM PDT 24 |
Peak memory | 386672 kb |
Host | smart-0f022f5f-a84d-4b59-a140-a27e82356f45 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2829767164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2829767164 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_384.3319490353 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 394299658046 ps |
CPU time | 1711.14 seconds |
Started | Jul 13 05:24:44 PM PDT 24 |
Finished | Jul 13 05:53:16 PM PDT 24 |
Peak memory | 339472 kb |
Host | smart-a4dc1c81-3b9d-4edc-9b36-6073e427101e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3319490353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.3319490353 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_512.2678399827 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 174601057148 ps |
CPU time | 1276.66 seconds |
Started | Jul 13 05:24:43 PM PDT 24 |
Finished | Jul 13 05:46:00 PM PDT 24 |
Peak memory | 301092 kb |
Host | smart-6bd443df-2cc9-497f-a495-d89968d417b9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2678399827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2678399827 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_shake_128.250825028 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 250416307983 ps |
CPU time | 4678.26 seconds |
Started | Jul 13 05:24:45 PM PDT 24 |
Finished | Jul 13 06:42:44 PM PDT 24 |
Peak memory | 653420 kb |
Host | smart-c271b4e7-dabf-4811-af22-e56b88b278f9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=250825028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.250825028 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/49.kmac_test_vectors_shake_256.3768418804 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 1456513903037 ps |
CPU time | 5372.96 seconds |
Started | Jul 13 05:24:46 PM PDT 24 |
Finished | Jul 13 06:54:20 PM PDT 24 |
Peak memory | 569480 kb |
Host | smart-5fe2c17f-4d25-453f-94db-c4fda2a77fb4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3768418804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3768418804 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/49.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/5.kmac_alert_test.534619081 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 49952907 ps |
CPU time | 0.92 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:07:12 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-42d90ff1-24a1-4009-b198-83855afd0ea9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534619081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.534619081 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_alert_test/latest |
Test location | /workspace/coverage/default/5.kmac_app.1334745337 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 6907457535 ps |
CPU time | 58.21 seconds |
Started | Jul 13 05:06:47 PM PDT 24 |
Finished | Jul 13 05:07:46 PM PDT 24 |
Peak memory | 228300 kb |
Host | smart-7feef2b2-a6f0-42c8-8f13-3ffc57b3d43a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334745337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1334745337 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_app/latest |
Test location | /workspace/coverage/default/5.kmac_app_with_partial_data.3753236210 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 3768789152 ps |
CPU time | 96.14 seconds |
Started | Jul 13 05:06:48 PM PDT 24 |
Finished | Jul 13 05:08:24 PM PDT 24 |
Peak memory | 232308 kb |
Host | smart-56ed4523-f5b6-4984-aecd-803d560b66e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753236210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3753236210 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/5.kmac_burst_write.1421548867 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 47278178774 ps |
CPU time | 881.1 seconds |
Started | Jul 13 05:06:47 PM PDT 24 |
Finished | Jul 13 05:21:28 PM PDT 24 |
Peak memory | 237872 kb |
Host | smart-f1f35761-bdd0-4f63-bcd4-0f30fb6facfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421548867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1421548867 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_burst_write/latest |
Test location | /workspace/coverage/default/5.kmac_edn_timeout_error.1001129457 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 910330643 ps |
CPU time | 31.27 seconds |
Started | Jul 13 05:06:58 PM PDT 24 |
Finished | Jul 13 05:07:30 PM PDT 24 |
Peak memory | 233688 kb |
Host | smart-1edce9bb-01f2-41f7-8a07-6c9e2fbb00d5 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1001129457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1001129457 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/5.kmac_entropy_mode_error.2360690972 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 177695763 ps |
CPU time | 1.35 seconds |
Started | Jul 13 05:07:00 PM PDT 24 |
Finished | Jul 13 05:07:02 PM PDT 24 |
Peak memory | 218348 kb |
Host | smart-27db9345-430f-4d70-94e4-c4797edf94ba |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2360690972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2360690972 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/5.kmac_entropy_ready_error.1003328963 |
Short name | T1050 |
Test name | |
Test status | |
Simulation time | 663857567 ps |
CPU time | 10.49 seconds |
Started | Jul 13 05:06:59 PM PDT 24 |
Finished | Jul 13 05:07:10 PM PDT 24 |
Peak memory | 226616 kb |
Host | smart-bd92a3e4-1486-4b0b-963c-c88c24d91edb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003328963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1003328963 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/5.kmac_error.957512083 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 20389912163 ps |
CPU time | 420.78 seconds |
Started | Jul 13 05:07:00 PM PDT 24 |
Finished | Jul 13 05:14:01 PM PDT 24 |
Peak memory | 267600 kb |
Host | smart-da75486a-f068-4656-bd0a-77cf0c1714a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957512083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.957512083 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_error/latest |
Test location | /workspace/coverage/default/5.kmac_key_error.3444979537 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 1420267995 ps |
CPU time | 11.8 seconds |
Started | Jul 13 05:07:00 PM PDT 24 |
Finished | Jul 13 05:07:12 PM PDT 24 |
Peak memory | 224068 kb |
Host | smart-888b325f-e8bc-4ae4-8f4f-dfeff0c8facc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444979537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3444979537 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_key_error/latest |
Test location | /workspace/coverage/default/5.kmac_lc_escalation.3214696701 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 39497720 ps |
CPU time | 1.14 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:07:12 PM PDT 24 |
Peak memory | 226488 kb |
Host | smart-5428e43f-e9ec-438b-b80e-ccb412040589 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214696701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3214696701 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/5.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/5.kmac_long_msg_and_output.3297674399 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 222794044941 ps |
CPU time | 2239.52 seconds |
Started | Jul 13 05:06:35 PM PDT 24 |
Finished | Jul 13 05:43:55 PM PDT 24 |
Peak memory | 432168 kb |
Host | smart-bbd8aacf-7534-4d40-865b-bdaf7832e591 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297674399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an d_output.3297674399 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/5.kmac_mubi.316038477 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 11839977416 ps |
CPU time | 276.09 seconds |
Started | Jul 13 05:06:59 PM PDT 24 |
Finished | Jul 13 05:11:35 PM PDT 24 |
Peak memory | 245764 kb |
Host | smart-0efbe18d-2499-42d8-a3ee-b25620e60a0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316038477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.316038477 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_mubi/latest |
Test location | /workspace/coverage/default/5.kmac_sideload.769763178 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 9466296028 ps |
CPU time | 390.6 seconds |
Started | Jul 13 05:06:48 PM PDT 24 |
Finished | Jul 13 05:13:19 PM PDT 24 |
Peak memory | 252492 kb |
Host | smart-7c9f90b5-0529-4d2f-bc35-119098c4e017 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769763178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.769763178 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_sideload/latest |
Test location | /workspace/coverage/default/5.kmac_smoke.1183435417 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 2293267157 ps |
CPU time | 45.8 seconds |
Started | Jul 13 05:06:35 PM PDT 24 |
Finished | Jul 13 05:07:21 PM PDT 24 |
Peak memory | 218772 kb |
Host | smart-ee56d649-7e76-4c43-9977-2e2214d6b405 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183435417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1183435417 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_smoke/latest |
Test location | /workspace/coverage/default/5.kmac_stress_all.862509580 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 98893629371 ps |
CPU time | 267.24 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:11:38 PM PDT 24 |
Peak memory | 276088 kb |
Host | smart-4f485f38-3706-4456-b887-8cc692a2174b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=862509580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.862509580 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_stress_all/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_kmac.3306420726 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 116234456 ps |
CPU time | 6.04 seconds |
Started | Jul 13 05:06:49 PM PDT 24 |
Finished | Jul 13 05:06:55 PM PDT 24 |
Peak memory | 219468 kb |
Host | smart-5ea969e3-3dc7-4eb2-894f-0ee3204b412e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306420726 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.kmac_test_vectors_kmac.3306420726 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.70235377 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 949021656 ps |
CPU time | 6.3 seconds |
Started | Jul 13 05:06:47 PM PDT 24 |
Finished | Jul 13 05:06:54 PM PDT 24 |
Peak memory | 218364 kb |
Host | smart-50968d9f-e91a-4c56-b980-0405f4baa9b1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70235377 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.kmac_test_vectors_kmac_xof.70235377 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2329694366 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 68364459437 ps |
CPU time | 2308.97 seconds |
Started | Jul 13 05:06:47 PM PDT 24 |
Finished | Jul 13 05:45:16 PM PDT 24 |
Peak memory | 401408 kb |
Host | smart-74200276-bae7-4a1c-832e-7bb3b50b5723 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2329694366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2329694366 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_256.4135130233 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 23847050810 ps |
CPU time | 1934.29 seconds |
Started | Jul 13 05:06:47 PM PDT 24 |
Finished | Jul 13 05:39:02 PM PDT 24 |
Peak memory | 381208 kb |
Host | smart-ea00028e-3f4d-43ca-8058-60d3ffef4b3d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4135130233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.4135130233 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_384.2898691171 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 254349433569 ps |
CPU time | 1661.52 seconds |
Started | Jul 13 05:06:46 PM PDT 24 |
Finished | Jul 13 05:34:28 PM PDT 24 |
Peak memory | 339676 kb |
Host | smart-07936213-068b-4a3e-b568-fa69bce91b0c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2898691171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2898691171 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_512.967782391 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 56213559611 ps |
CPU time | 1235.22 seconds |
Started | Jul 13 05:06:49 PM PDT 24 |
Finished | Jul 13 05:27:24 PM PDT 24 |
Peak memory | 299240 kb |
Host | smart-25aac8b4-cd70-40a4-9272-3e64cd3ccca5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=967782391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.967782391 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/5.kmac_test_vectors_shake_128.1476306516 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 371390560349 ps |
CPU time | 5701.37 seconds |
Started | Jul 13 05:06:49 PM PDT 24 |
Finished | Jul 13 06:41:51 PM PDT 24 |
Peak memory | 659772 kb |
Host | smart-e2307ffe-4411-428e-a522-f3d8f0467a84 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1476306516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1476306516 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/5.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/6.kmac_alert_test.2250104951 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 31812123 ps |
CPU time | 0.79 seconds |
Started | Jul 13 05:07:29 PM PDT 24 |
Finished | Jul 13 05:07:31 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-8352aebc-841d-43bb-a40a-14954f82feba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250104951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2250104951 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_alert_test/latest |
Test location | /workspace/coverage/default/6.kmac_app.2843902349 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 45916805600 ps |
CPU time | 61.47 seconds |
Started | Jul 13 05:07:21 PM PDT 24 |
Finished | Jul 13 05:08:23 PM PDT 24 |
Peak memory | 237060 kb |
Host | smart-d18eb645-c8f0-4cfb-a2ae-d18e8b28dbe8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843902349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2843902349 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_app/latest |
Test location | /workspace/coverage/default/6.kmac_app_with_partial_data.586392404 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 17487741259 ps |
CPU time | 357.24 seconds |
Started | Jul 13 05:07:19 PM PDT 24 |
Finished | Jul 13 05:13:17 PM PDT 24 |
Peak memory | 250084 kb |
Host | smart-e3148fc8-bde6-43c1-8a5a-86dbc293809a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586392404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.586392404 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/6.kmac_burst_write.227046437 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 28778416073 ps |
CPU time | 749.2 seconds |
Started | Jul 13 05:07:11 PM PDT 24 |
Finished | Jul 13 05:19:41 PM PDT 24 |
Peak memory | 233860 kb |
Host | smart-81e0b248-72b8-4754-8343-7c3a10bb69d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227046437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.227046437 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_burst_write/latest |
Test location | /workspace/coverage/default/6.kmac_edn_timeout_error.497351032 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 414558228 ps |
CPU time | 10.23 seconds |
Started | Jul 13 05:07:29 PM PDT 24 |
Finished | Jul 13 05:07:40 PM PDT 24 |
Peak memory | 221892 kb |
Host | smart-2d45ba8b-1dc7-4b09-9035-ef87b20ac5b5 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=497351032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.497351032 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/6.kmac_entropy_mode_error.796737224 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 69338326 ps |
CPU time | 1.04 seconds |
Started | Jul 13 05:07:31 PM PDT 24 |
Finished | Jul 13 05:07:33 PM PDT 24 |
Peak memory | 218180 kb |
Host | smart-fb8e3770-a82d-4d23-b408-1074cc9f16b8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=796737224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.796737224 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/6.kmac_entropy_ready_error.49076768 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 3874136429 ps |
CPU time | 43.34 seconds |
Started | Jul 13 05:07:28 PM PDT 24 |
Finished | Jul 13 05:08:12 PM PDT 24 |
Peak memory | 226632 kb |
Host | smart-2879fef6-57d0-40d0-bd81-534201a507dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49076768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.49076768 +enable_masking= 1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/6.kmac_entropy_refresh.515409024 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 23169908802 ps |
CPU time | 370.25 seconds |
Started | Jul 13 05:07:20 PM PDT 24 |
Finished | Jul 13 05:13:30 PM PDT 24 |
Peak memory | 251852 kb |
Host | smart-2cd08906-b36f-4c77-a077-15402fde13a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515409024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.515409024 +enable_masking=1 +sw_ key_masked=0 |
Directory | /workspace/6.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/6.kmac_error.1286177152 |
Short name | T1059 |
Test name | |
Test status | |
Simulation time | 8004568996 ps |
CPU time | 209.75 seconds |
Started | Jul 13 05:07:20 PM PDT 24 |
Finished | Jul 13 05:10:50 PM PDT 24 |
Peak memory | 251144 kb |
Host | smart-357df8a9-243e-48e5-8249-1a9c1faf88ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286177152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1286177152 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_error/latest |
Test location | /workspace/coverage/default/6.kmac_key_error.2318210955 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 798875269 ps |
CPU time | 4.05 seconds |
Started | Jul 13 05:07:29 PM PDT 24 |
Finished | Jul 13 05:07:34 PM PDT 24 |
Peak memory | 223160 kb |
Host | smart-ad534084-f0fb-4182-8f9c-3048ddda9cfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318210955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2318210955 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_key_error/latest |
Test location | /workspace/coverage/default/6.kmac_long_msg_and_output.1952390308 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 22690424607 ps |
CPU time | 792.73 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:20:23 PM PDT 24 |
Peak memory | 284124 kb |
Host | smart-04d4a790-864c-4264-a8cf-1c2a107e82cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952390308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.1952390308 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/6.kmac_mubi.2854443666 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 573627205 ps |
CPU time | 7.28 seconds |
Started | Jul 13 05:07:19 PM PDT 24 |
Finished | Jul 13 05:07:27 PM PDT 24 |
Peak memory | 226836 kb |
Host | smart-f35b7215-1a00-43ba-b7cc-121d7cf49c1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854443666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2854443666 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_mubi/latest |
Test location | /workspace/coverage/default/6.kmac_sideload.2492214270 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 20864331188 ps |
CPU time | 447.19 seconds |
Started | Jul 13 05:07:11 PM PDT 24 |
Finished | Jul 13 05:14:38 PM PDT 24 |
Peak memory | 254240 kb |
Host | smart-83d7b104-1866-487d-9527-4e901fd49117 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492214270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2492214270 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_sideload/latest |
Test location | /workspace/coverage/default/6.kmac_smoke.3877835870 |
Short name | T1064 |
Test name | |
Test status | |
Simulation time | 134994613 ps |
CPU time | 4.76 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:07:15 PM PDT 24 |
Peak memory | 223260 kb |
Host | smart-6bc5a896-fa60-4582-85a0-96fc76678f7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877835870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3877835870 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_smoke/latest |
Test location | /workspace/coverage/default/6.kmac_stress_all.3331704310 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 101588464923 ps |
CPU time | 604.8 seconds |
Started | Jul 13 05:07:31 PM PDT 24 |
Finished | Jul 13 05:17:36 PM PDT 24 |
Peak memory | 283892 kb |
Host | smart-7e7a7b6e-7642-4e11-bffa-dd65054cf34a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3331704310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3331704310 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_stress_all/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_kmac.3573232574 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 250031533 ps |
CPU time | 5.8 seconds |
Started | Jul 13 05:07:20 PM PDT 24 |
Finished | Jul 13 05:07:26 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-b7a23660-b946-4a89-be1b-ecf7f67929b1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573232574 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.3573232574 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.4209640885 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 540636501 ps |
CPU time | 6.38 seconds |
Started | Jul 13 05:07:21 PM PDT 24 |
Finished | Jul 13 05:07:28 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-5a4d26cc-84bc-4de4-b776-0f9eb9f737f4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209640885 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.4209640885 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2247471239 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 22481203510 ps |
CPU time | 1908.21 seconds |
Started | Jul 13 05:07:09 PM PDT 24 |
Finished | Jul 13 05:38:58 PM PDT 24 |
Peak memory | 401668 kb |
Host | smart-3bcaaf3f-2bac-4e3a-b285-94acd9278257 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2247471239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2247471239 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2355745126 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 62290449156 ps |
CPU time | 2025.87 seconds |
Started | Jul 13 05:07:09 PM PDT 24 |
Finished | Jul 13 05:40:56 PM PDT 24 |
Peak memory | 386308 kb |
Host | smart-42fce869-35b5-457d-9ed1-7937cfc99afa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2355745126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2355745126 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_384.48254560 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 176125897924 ps |
CPU time | 1756.06 seconds |
Started | Jul 13 05:07:10 PM PDT 24 |
Finished | Jul 13 05:36:26 PM PDT 24 |
Peak memory | 340196 kb |
Host | smart-c375693f-a777-430b-ab39-beda46966590 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=48254560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.48254560 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_512.920041942 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 136058667863 ps |
CPU time | 1210.66 seconds |
Started | Jul 13 05:07:21 PM PDT 24 |
Finished | Jul 13 05:27:33 PM PDT 24 |
Peak memory | 296352 kb |
Host | smart-d18476f3-255c-477d-aa3c-50084f1fa52b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=920041942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.920041942 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_shake_128.1458319973 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 245172823962 ps |
CPU time | 4949.44 seconds |
Started | Jul 13 05:07:21 PM PDT 24 |
Finished | Jul 13 06:29:51 PM PDT 24 |
Peak memory | 646228 kb |
Host | smart-c3b338b7-db39-487f-9afe-2e55a3d29409 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1458319973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1458319973 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/6.kmac_test_vectors_shake_256.2849700423 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 609139270136 ps |
CPU time | 4855.74 seconds |
Started | Jul 13 05:07:21 PM PDT 24 |
Finished | Jul 13 06:28:17 PM PDT 24 |
Peak memory | 575936 kb |
Host | smart-75339302-34de-4ae3-9ea5-6a7e09b01559 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2849700423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2849700423 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/6.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/7.kmac_alert_test.3327842290 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 22145255 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:07:59 PM PDT 24 |
Finished | Jul 13 05:08:00 PM PDT 24 |
Peak memory | 218188 kb |
Host | smart-9a9d8083-f8da-427f-8080-77fc0c5a93a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327842290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3327842290 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_alert_test/latest |
Test location | /workspace/coverage/default/7.kmac_app.2955556069 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 5007651698 ps |
CPU time | 56.45 seconds |
Started | Jul 13 05:07:51 PM PDT 24 |
Finished | Jul 13 05:08:48 PM PDT 24 |
Peak memory | 229808 kb |
Host | smart-21f5e0fe-e49a-456a-ab2c-cf2ae5f8a2b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955556069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2955556069 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_app/latest |
Test location | /workspace/coverage/default/7.kmac_app_with_partial_data.572943076 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 7413716254 ps |
CPU time | 320.93 seconds |
Started | Jul 13 05:07:52 PM PDT 24 |
Finished | Jul 13 05:13:13 PM PDT 24 |
Peak memory | 249544 kb |
Host | smart-180a47f1-5637-4f16-9cd1-708d3f123be1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572943076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.572943076 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/7.kmac_burst_write.2252365975 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 721959247 ps |
CPU time | 76.9 seconds |
Started | Jul 13 05:07:39 PM PDT 24 |
Finished | Jul 13 05:08:56 PM PDT 24 |
Peak memory | 219892 kb |
Host | smart-3cfa1298-7f7a-49ac-a274-3b83aa4bff24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252365975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2252365975 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_burst_write/latest |
Test location | /workspace/coverage/default/7.kmac_edn_timeout_error.1733395914 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 1768859215 ps |
CPU time | 46.64 seconds |
Started | Jul 13 05:08:01 PM PDT 24 |
Finished | Jul 13 05:08:48 PM PDT 24 |
Peak memory | 228264 kb |
Host | smart-1cb77f78-7101-4dc1-b308-410413420551 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1733395914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1733395914 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/7.kmac_entropy_mode_error.2749094050 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 152144502 ps |
CPU time | 1.14 seconds |
Started | Jul 13 05:07:59 PM PDT 24 |
Finished | Jul 13 05:08:01 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-76d16f19-044f-492e-82e5-9a480dfc7761 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2749094050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2749094050 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/7.kmac_entropy_ready_error.728697476 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 1583040199 ps |
CPU time | 19.64 seconds |
Started | Jul 13 05:07:58 PM PDT 24 |
Finished | Jul 13 05:08:18 PM PDT 24 |
Peak memory | 226560 kb |
Host | smart-904c61ba-8858-4f77-8f94-20216d9b4457 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728697476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.728697476 +enable_maskin g=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/7.kmac_entropy_refresh.46598674 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 820924695 ps |
CPU time | 15.43 seconds |
Started | Jul 13 05:07:51 PM PDT 24 |
Finished | Jul 13 05:08:07 PM PDT 24 |
Peak memory | 236408 kb |
Host | smart-d7fcc44f-a0e7-46c2-b13b-443bd60b9f69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46598674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.46598674 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/7.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/7.kmac_error.2639705252 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 56795915051 ps |
CPU time | 341.69 seconds |
Started | Jul 13 05:07:51 PM PDT 24 |
Finished | Jul 13 05:13:33 PM PDT 24 |
Peak memory | 257720 kb |
Host | smart-8ffa425c-64f7-42d3-9242-4e497402338a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639705252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2639705252 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_error/latest |
Test location | /workspace/coverage/default/7.kmac_key_error.3818483515 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 1896756406 ps |
CPU time | 3.85 seconds |
Started | Jul 13 05:07:50 PM PDT 24 |
Finished | Jul 13 05:07:54 PM PDT 24 |
Peak memory | 222708 kb |
Host | smart-3c6762c9-a38e-4e73-a26a-cef27931fbd9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818483515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3818483515 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_key_error/latest |
Test location | /workspace/coverage/default/7.kmac_lc_escalation.472871896 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 80264154 ps |
CPU time | 1.48 seconds |
Started | Jul 13 05:08:01 PM PDT 24 |
Finished | Jul 13 05:08:02 PM PDT 24 |
Peak memory | 226608 kb |
Host | smart-7ef16783-14da-4aa2-baa5-cfb0431698d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472871896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.472871896 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/7.kmac_long_msg_and_output.3475406422 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 60462047927 ps |
CPU time | 1686.32 seconds |
Started | Jul 13 05:07:29 PM PDT 24 |
Finished | Jul 13 05:35:36 PM PDT 24 |
Peak memory | 343924 kb |
Host | smart-298c1c08-1cc6-43fc-b0d1-ce3b8bc00f4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475406422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.3475406422 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/7.kmac_mubi.4074315371 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 9598058672 ps |
CPU time | 111.32 seconds |
Started | Jul 13 05:07:53 PM PDT 24 |
Finished | Jul 13 05:09:44 PM PDT 24 |
Peak memory | 236316 kb |
Host | smart-c69852b3-a9e7-494d-88ae-9fcbda9ebd92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074315371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.4074315371 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_mubi/latest |
Test location | /workspace/coverage/default/7.kmac_sideload.1415010917 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 8651927855 ps |
CPU time | 322.27 seconds |
Started | Jul 13 05:07:38 PM PDT 24 |
Finished | Jul 13 05:13:01 PM PDT 24 |
Peak memory | 246428 kb |
Host | smart-b7d66eff-e9f3-4dbd-afa9-08e172a7bef0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415010917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1415010917 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_sideload/latest |
Test location | /workspace/coverage/default/7.kmac_smoke.164531717 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 4199809375 ps |
CPU time | 82.14 seconds |
Started | Jul 13 05:07:29 PM PDT 24 |
Finished | Jul 13 05:08:51 PM PDT 24 |
Peak memory | 226720 kb |
Host | smart-67753495-c579-4ffe-ac0d-6991e4768bf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164531717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.164531717 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_smoke/latest |
Test location | /workspace/coverage/default/7.kmac_stress_all.1257567580 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 10856730166 ps |
CPU time | 298.07 seconds |
Started | Jul 13 05:07:59 PM PDT 24 |
Finished | Jul 13 05:12:58 PM PDT 24 |
Peak memory | 285208 kb |
Host | smart-41488ce7-99d8-4b12-b4f2-8abfdd31e954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1257567580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1257567580 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_stress_all/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_kmac.3511885655 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 215158780 ps |
CPU time | 6.07 seconds |
Started | Jul 13 05:07:51 PM PDT 24 |
Finished | Jul 13 05:07:57 PM PDT 24 |
Peak memory | 218788 kb |
Host | smart-79a1b6c0-d9c9-4569-bb4a-f9a0af2515d1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511885655 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.3511885655 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.4151671795 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 248977058 ps |
CPU time | 6.01 seconds |
Started | Jul 13 05:07:51 PM PDT 24 |
Finished | Jul 13 05:07:58 PM PDT 24 |
Peak memory | 218476 kb |
Host | smart-56fb98b0-b752-4568-9106-0c886be5ff05 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151671795 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.4151671795 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1396626345 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 992026804659 ps |
CPU time | 2330.13 seconds |
Started | Jul 13 05:07:40 PM PDT 24 |
Finished | Jul 13 05:46:30 PM PDT 24 |
Peak memory | 404928 kb |
Host | smart-a3183a9c-e3f2-4ee0-afa8-f88d0b013891 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1396626345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1396626345 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_256.1588555437 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 81116264311 ps |
CPU time | 1661.02 seconds |
Started | Jul 13 05:07:38 PM PDT 24 |
Finished | Jul 13 05:35:20 PM PDT 24 |
Peak memory | 387564 kb |
Host | smart-cd7e2739-a742-41a1-98bc-388caa354249 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1588555437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1588555437 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1408720058 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 23171552265 ps |
CPU time | 1523.73 seconds |
Started | Jul 13 05:07:38 PM PDT 24 |
Finished | Jul 13 05:33:03 PM PDT 24 |
Peak memory | 343364 kb |
Host | smart-d49ee344-7d12-4c4b-8b56-312c38c279dc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1408720058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1408720058 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_512.20416507 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 34934819327 ps |
CPU time | 1165.01 seconds |
Started | Jul 13 05:07:40 PM PDT 24 |
Finished | Jul 13 05:27:05 PM PDT 24 |
Peak memory | 300784 kb |
Host | smart-960822f9-01df-45f4-a04f-604653f8d573 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=20416507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.20416507 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_shake_128.3853966597 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 184714815928 ps |
CPU time | 5549.62 seconds |
Started | Jul 13 05:07:39 PM PDT 24 |
Finished | Jul 13 06:40:09 PM PDT 24 |
Peak memory | 643092 kb |
Host | smart-44dd4f0a-b865-466f-becc-63fb81879fca |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3853966597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3853966597 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/7.kmac_test_vectors_shake_256.1935245067 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 657731167744 ps |
CPU time | 4566.68 seconds |
Started | Jul 13 05:07:38 PM PDT 24 |
Finished | Jul 13 06:23:45 PM PDT 24 |
Peak memory | 567032 kb |
Host | smart-2b74cdff-21fd-46e1-9f6a-a9c407bf9649 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1935245067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1935245067 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/7.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/8.kmac_alert_test.3601541786 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 17689387 ps |
CPU time | 0.84 seconds |
Started | Jul 13 05:08:27 PM PDT 24 |
Finished | Jul 13 05:08:29 PM PDT 24 |
Peak memory | 218240 kb |
Host | smart-d0c8aebe-4cd8-42da-8967-1e11b7917cfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601541786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3601541786 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_alert_test/latest |
Test location | /workspace/coverage/default/8.kmac_app.3775209148 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 8103240454 ps |
CPU time | 127.47 seconds |
Started | Jul 13 05:08:20 PM PDT 24 |
Finished | Jul 13 05:10:28 PM PDT 24 |
Peak memory | 234796 kb |
Host | smart-2ff07af1-7b32-4214-8e8d-a4fea361b37a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775209148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3775209148 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_app/latest |
Test location | /workspace/coverage/default/8.kmac_app_with_partial_data.983391304 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 25938561241 ps |
CPU time | 334.97 seconds |
Started | Jul 13 05:08:20 PM PDT 24 |
Finished | Jul 13 05:13:55 PM PDT 24 |
Peak memory | 251424 kb |
Host | smart-932fbecf-4590-431c-b209-ea23f2f0b5e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983391304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.983391304 +enable_ma sking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/8.kmac_burst_write.360747650 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 5257669267 ps |
CPU time | 188.67 seconds |
Started | Jul 13 05:08:10 PM PDT 24 |
Finished | Jul 13 05:11:19 PM PDT 24 |
Peak memory | 227724 kb |
Host | smart-b30137fe-c02b-4d90-9075-82daa02b62cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360747650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.360747650 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_burst_write/latest |
Test location | /workspace/coverage/default/8.kmac_edn_timeout_error.1813837796 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 20511096 ps |
CPU time | 1.08 seconds |
Started | Jul 13 05:08:19 PM PDT 24 |
Finished | Jul 13 05:08:21 PM PDT 24 |
Peak memory | 218352 kb |
Host | smart-e048c30e-0663-45cc-aac5-225c05edda6f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1813837796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1813837796 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/8.kmac_entropy_mode_error.2129870000 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 14412094 ps |
CPU time | 0.86 seconds |
Started | Jul 13 05:08:19 PM PDT 24 |
Finished | Jul 13 05:08:20 PM PDT 24 |
Peak memory | 218072 kb |
Host | smart-64a48517-c210-45a5-9d56-c9d9385ed72b |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2129870000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2129870000 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/8.kmac_entropy_ready_error.3017253585 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 25780908324 ps |
CPU time | 71.19 seconds |
Started | Jul 13 05:08:19 PM PDT 24 |
Finished | Jul 13 05:09:31 PM PDT 24 |
Peak memory | 220404 kb |
Host | smart-d42d90ae-07d8-49aa-979e-8e9abccee550 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017253585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3017253585 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/8.kmac_entropy_refresh.1469795869 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 2211966110 ps |
CPU time | 52.68 seconds |
Started | Jul 13 05:08:20 PM PDT 24 |
Finished | Jul 13 05:09:13 PM PDT 24 |
Peak memory | 227644 kb |
Host | smart-b8234f7e-e9ff-44c9-a569-967e70c0ec47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469795869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1469795869 +enable_masking=1 +s w_key_masked=0 |
Directory | /workspace/8.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/8.kmac_key_error.3929442413 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 335802222 ps |
CPU time | 3.03 seconds |
Started | Jul 13 05:08:18 PM PDT 24 |
Finished | Jul 13 05:08:22 PM PDT 24 |
Peak memory | 222516 kb |
Host | smart-847649cc-1acd-4cbf-a7e5-d548404585c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929442413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3929442413 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_key_error/latest |
Test location | /workspace/coverage/default/8.kmac_lc_escalation.1626524643 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 627432189 ps |
CPU time | 22.65 seconds |
Started | Jul 13 05:08:28 PM PDT 24 |
Finished | Jul 13 05:08:51 PM PDT 24 |
Peak memory | 234940 kb |
Host | smart-bfe8c471-cabd-40d3-8b0c-e90835efd168 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626524643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1626524643 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/8.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/8.kmac_long_msg_and_output.3465017392 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 435384522052 ps |
CPU time | 3060.87 seconds |
Started | Jul 13 05:08:00 PM PDT 24 |
Finished | Jul 13 05:59:02 PM PDT 24 |
Peak memory | 442184 kb |
Host | smart-10ce8ea6-3983-4425-ba33-6a3e85004cdb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465017392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.3465017392 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/8.kmac_mubi.802849101 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 4639152898 ps |
CPU time | 119.26 seconds |
Started | Jul 13 05:08:19 PM PDT 24 |
Finished | Jul 13 05:10:18 PM PDT 24 |
Peak memory | 234996 kb |
Host | smart-b88920f8-ef9b-43ab-b899-1f75a2db6630 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802849101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.802849101 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_mubi/latest |
Test location | /workspace/coverage/default/8.kmac_sideload.2225525829 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 78416070889 ps |
CPU time | 463.59 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 05:15:53 PM PDT 24 |
Peak memory | 255252 kb |
Host | smart-11f6a985-3387-4017-b15f-98fb7e37f6ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225525829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2225525829 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_sideload/latest |
Test location | /workspace/coverage/default/8.kmac_smoke.2985133788 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 1428874903 ps |
CPU time | 55.93 seconds |
Started | Jul 13 05:07:58 PM PDT 24 |
Finished | Jul 13 05:08:55 PM PDT 24 |
Peak memory | 226644 kb |
Host | smart-ae71011d-6f4e-46f9-8f4d-a7184aa84e49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985133788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2985133788 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_smoke/latest |
Test location | /workspace/coverage/default/8.kmac_stress_all.2270309899 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 46965050164 ps |
CPU time | 1935.37 seconds |
Started | Jul 13 05:08:28 PM PDT 24 |
Finished | Jul 13 05:40:44 PM PDT 24 |
Peak memory | 450680 kb |
Host | smart-2abca54e-4a78-4d3e-b3ab-4f0f4c162692 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2270309899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2270309899 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_stress_all/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_kmac.1395214958 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 281191546 ps |
CPU time | 7.59 seconds |
Started | Jul 13 05:08:10 PM PDT 24 |
Finished | Jul 13 05:08:18 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-e95a456f-5b91-4864-a2ba-7f994873dfd1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395214958 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.1395214958 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.596004071 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 117134476 ps |
CPU time | 5.4 seconds |
Started | Jul 13 05:08:19 PM PDT 24 |
Finished | Jul 13 05:08:25 PM PDT 24 |
Peak memory | 218516 kb |
Host | smart-c4204c44-da11-4fda-8241-932cce3a25b0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596004071 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.kmac_test_vectors_kmac_xof.596004071 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_224.1422013241 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 84994523906 ps |
CPU time | 1980.22 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 05:41:10 PM PDT 24 |
Peak memory | 397424 kb |
Host | smart-eef466c0-0171-4c11-a79a-053469ad35d7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1422013241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1422013241 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2210499940 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 95818742262 ps |
CPU time | 2244.15 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 05:45:34 PM PDT 24 |
Peak memory | 386496 kb |
Host | smart-9b4307a0-ae94-4dc8-9613-93f517b9ac0d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2210499940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2210499940 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_384.4176224479 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 48911091527 ps |
CPU time | 1567.89 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 05:34:17 PM PDT 24 |
Peak memory | 334696 kb |
Host | smart-952b638a-5532-4dae-b314-9bef0fb43649 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4176224479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.4176224479 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1934043446 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 50593107917 ps |
CPU time | 1383.32 seconds |
Started | Jul 13 05:08:10 PM PDT 24 |
Finished | Jul 13 05:31:14 PM PDT 24 |
Peak memory | 304260 kb |
Host | smart-c91e4dfc-29b4-44c1-85dc-a53f795e9bba |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1934043446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1934043446 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_shake_128.747496046 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 289218510059 ps |
CPU time | 5617.51 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 06:41:48 PM PDT 24 |
Peak memory | 654476 kb |
Host | smart-e101c76f-4fd1-4f75-bff9-2a078e65ae61 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=747496046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.747496046 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/8.kmac_test_vectors_shake_256.1834244825 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 629632019916 ps |
CPU time | 4924.48 seconds |
Started | Jul 13 05:08:09 PM PDT 24 |
Finished | Jul 13 06:30:15 PM PDT 24 |
Peak memory | 573248 kb |
Host | smart-ad27758e-64ac-4374-8f55-ce04784f8a36 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1834244825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1834244825 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/8.kmac_test_vectors_shake_256/latest |
Test location | /workspace/coverage/default/9.kmac_alert_test.4005236541 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 16048523 ps |
CPU time | 0.83 seconds |
Started | Jul 13 05:08:59 PM PDT 24 |
Finished | Jul 13 05:09:00 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-8be1805a-2a47-40bd-836f-8cae582b4bd3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005236541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4005236541 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_alert_test/latest |
Test location | /workspace/coverage/default/9.kmac_app.3075971264 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 850829219 ps |
CPU time | 49.18 seconds |
Started | Jul 13 05:08:47 PM PDT 24 |
Finished | Jul 13 05:09:36 PM PDT 24 |
Peak memory | 226484 kb |
Host | smart-60f163a2-2e29-439b-9332-c0a734d8633b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075971264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3075971264 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_app/latest |
Test location | /workspace/coverage/default/9.kmac_app_with_partial_data.1697309979 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 18188835421 ps |
CPU time | 215.95 seconds |
Started | Jul 13 05:08:47 PM PDT 24 |
Finished | Jul 13 05:12:23 PM PDT 24 |
Peak memory | 242780 kb |
Host | smart-bbb6bf99-1ad6-472f-9f91-c1c07c87bfe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697309979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1697309979 +enable_ masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_app_with_partial_data/latest |
Test location | /workspace/coverage/default/9.kmac_burst_write.3675126499 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 99787950816 ps |
CPU time | 1334.12 seconds |
Started | Jul 13 05:08:37 PM PDT 24 |
Finished | Jul 13 05:30:52 PM PDT 24 |
Peak memory | 238088 kb |
Host | smart-3635a762-fea7-4830-9f7e-7e5c0974f23f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675126499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3675126499 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_burst_write/latest |
Test location | /workspace/coverage/default/9.kmac_edn_timeout_error.3048863137 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 24869236 ps |
CPU time | 1.03 seconds |
Started | Jul 13 05:08:56 PM PDT 24 |
Finished | Jul 13 05:08:58 PM PDT 24 |
Peak memory | 218132 kb |
Host | smart-1ea29c59-a0d6-4a6b-bca0-c394edcc1dfc |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3048863137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3048863137 +enabl e_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_edn_timeout_error/latest |
Test location | /workspace/coverage/default/9.kmac_entropy_mode_error.3972657517 |
Short name | T1075 |
Test name | |
Test status | |
Simulation time | 36124358 ps |
CPU time | 1.22 seconds |
Started | Jul 13 05:08:56 PM PDT 24 |
Finished | Jul 13 05:08:58 PM PDT 24 |
Peak memory | 218356 kb |
Host | smart-85b28345-526c-40f1-a40c-d1acb8fdad13 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3972657517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3972657517 +ena ble_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_entropy_mode_error/latest |
Test location | /workspace/coverage/default/9.kmac_entropy_ready_error.3718013321 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 11289259991 ps |
CPU time | 71.51 seconds |
Started | Jul 13 05:08:57 PM PDT 24 |
Finished | Jul 13 05:10:09 PM PDT 24 |
Peak memory | 226600 kb |
Host | smart-e0b4c694-1e2e-4ac0-be00-117786e2b4d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718013321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3718013321 +enable_mask ing=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_entropy_ready_error/latest |
Test location | /workspace/coverage/default/9.kmac_entropy_refresh.2465737840 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 19112165703 ps |
CPU time | 393.99 seconds |
Started | Jul 13 05:08:59 PM PDT 24 |
Finished | Jul 13 05:15:34 PM PDT 24 |
Peak memory | 252380 kb |
Host | smart-67bd3eb5-0e47-40a6-ba71-5a65ed7b7cdf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465737840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2465737840 +enable_masking=1 +s w_key_masked=0 |
Directory | /workspace/9.kmac_entropy_refresh/latest |
Test location | /workspace/coverage/default/9.kmac_error.1497036617 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 33525308260 ps |
CPU time | 291.51 seconds |
Started | Jul 13 05:08:56 PM PDT 24 |
Finished | Jul 13 05:13:48 PM PDT 24 |
Peak memory | 259444 kb |
Host | smart-0b1efd4c-b7b4-4f67-9458-365ec473f52d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1497036617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1497036617 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_error/latest |
Test location | /workspace/coverage/default/9.kmac_key_error.708409595 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 1600748791 ps |
CPU time | 12.21 seconds |
Started | Jul 13 05:08:57 PM PDT 24 |
Finished | Jul 13 05:09:10 PM PDT 24 |
Peak memory | 225540 kb |
Host | smart-69b2bbd1-858d-4d06-8e4e-d6f58df7be1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708409595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.708409595 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_key_error/latest |
Test location | /workspace/coverage/default/9.kmac_lc_escalation.2636288806 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 149072489 ps |
CPU time | 1.37 seconds |
Started | Jul 13 05:08:57 PM PDT 24 |
Finished | Jul 13 05:08:59 PM PDT 24 |
Peak memory | 226508 kb |
Host | smart-952f7085-1a98-462b-9731-8bf56e81bbac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2636288806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2636288806 +enable_masking=1 +sw_ke y_masked=0 |
Directory | /workspace/9.kmac_lc_escalation/latest |
Test location | /workspace/coverage/default/9.kmac_long_msg_and_output.597964269 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 24223757470 ps |
CPU time | 1758.72 seconds |
Started | Jul 13 05:08:35 PM PDT 24 |
Finished | Jul 13 05:37:54 PM PDT 24 |
Peak memory | 383284 kb |
Host | smart-b42bc69b-8035-4bbf-ac69-a12903b7c274 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597964269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and _output.597964269 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_long_msg_and_output/latest |
Test location | /workspace/coverage/default/9.kmac_mubi.574304434 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 6907566722 ps |
CPU time | 159.86 seconds |
Started | Jul 13 05:08:58 PM PDT 24 |
Finished | Jul 13 05:11:38 PM PDT 24 |
Peak memory | 239392 kb |
Host | smart-7f9b032e-f017-4675-bc94-1310368ba389 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574304434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.574304434 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_mubi/latest |
Test location | /workspace/coverage/default/9.kmac_sideload.859233221 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 8019342311 ps |
CPU time | 343.96 seconds |
Started | Jul 13 05:08:36 PM PDT 24 |
Finished | Jul 13 05:14:20 PM PDT 24 |
Peak memory | 246240 kb |
Host | smart-15a140f1-7b9a-4aff-a89f-c34dc6d2f044 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859233221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.859233221 +enab le_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_sideload/latest |
Test location | /workspace/coverage/default/9.kmac_smoke.836405631 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 6860729821 ps |
CPU time | 65.87 seconds |
Started | Jul 13 05:08:28 PM PDT 24 |
Finished | Jul 13 05:09:35 PM PDT 24 |
Peak memory | 219140 kb |
Host | smart-2e079a76-b038-4de6-b5f0-9cae2f851048 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836405631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.836405631 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_smoke/latest |
Test location | /workspace/coverage/default/9.kmac_stress_all.2817150225 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 206512625 ps |
CPU time | 2.36 seconds |
Started | Jul 13 05:08:57 PM PDT 24 |
Finished | Jul 13 05:09:00 PM PDT 24 |
Peak memory | 218700 kb |
Host | smart-a3b1c5c4-b471-4cdf-9847-53f903b35a86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2817150225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2817150225 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_stress_all/latest |
Test location | /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1886243093 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 73941780057 ps |
CPU time | 587.08 seconds |
Started | Jul 13 05:09:00 PM PDT 24 |
Finished | Jul 13 05:18:48 PM PDT 24 |
Peak memory | 275428 kb |
Host | smart-f4aaa289-18b6-4563-89a3-2a9d8a00611a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1886243093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1886243093 +en able_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_kmac.3362495892 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 343731261 ps |
CPU time | 6.78 seconds |
Started | Jul 13 05:08:48 PM PDT 24 |
Finished | Jul 13 05:08:55 PM PDT 24 |
Peak memory | 218296 kb |
Host | smart-62b23898-270c-4ade-9c0e-77679ff8ad02 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362495892 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.kmac_test_vectors_kmac.3362495892 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_kmac/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3843184553 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 432347547 ps |
CPU time | 6.31 seconds |
Started | Jul 13 05:08:51 PM PDT 24 |
Finished | Jul 13 05:08:58 PM PDT 24 |
Peak memory | 219464 kb |
Host | smart-4b9cfa59-11bd-4586-8766-70be9c8ed718 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843184553 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3843184553 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_kmac_xof/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1028008530 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 139708839251 ps |
CPU time | 2310.15 seconds |
Started | Jul 13 05:08:34 PM PDT 24 |
Finished | Jul 13 05:47:05 PM PDT 24 |
Peak memory | 400776 kb |
Host | smart-a392b6bc-f93c-4f26-87ef-8153ca550078 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1028008530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1028008530 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_sha3_224/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_256.224766270 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 26280732229 ps |
CPU time | 1984.14 seconds |
Started | Jul 13 05:08:36 PM PDT 24 |
Finished | Jul 13 05:41:41 PM PDT 24 |
Peak memory | 382740 kb |
Host | smart-417b41ab-1c13-4245-af34-ba8c141d68b8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=224766270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.224766270 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_sha3_256/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_384.2034395069 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 70931157755 ps |
CPU time | 1521.04 seconds |
Started | Jul 13 05:08:36 PM PDT 24 |
Finished | Jul 13 05:33:57 PM PDT 24 |
Peak memory | 341340 kb |
Host | smart-527b90fd-13d0-4e26-898f-d68bcaca38be |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2034395069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2034395069 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_sha3_384/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2501034251 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 80607714805 ps |
CPU time | 1044.18 seconds |
Started | Jul 13 05:08:35 PM PDT 24 |
Finished | Jul 13 05:25:59 PM PDT 24 |
Peak memory | 300748 kb |
Host | smart-50d8b183-47ee-45bf-b994-2cd5887714f8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2501034251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2501034251 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_sha3_512/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_shake_128.507017100 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 215533092462 ps |
CPU time | 5250.73 seconds |
Started | Jul 13 05:08:37 PM PDT 24 |
Finished | Jul 13 06:36:09 PM PDT 24 |
Peak memory | 664512 kb |
Host | smart-33bf79de-1d80-4cdf-bbed-a32a851cf1a1 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=507017100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.507017100 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_shake_128/latest |
Test location | /workspace/coverage/default/9.kmac_test_vectors_shake_256.1554323678 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 238421427406 ps |
CPU time | 5264.62 seconds |
Started | Jul 13 05:08:48 PM PDT 24 |
Finished | Jul 13 06:36:33 PM PDT 24 |
Peak memory | 578876 kb |
Host | smart-2fd64a64-953b-41ff-84f9-aadb2c728528 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1554323678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1554323678 +enable_masking=1 +sw_key_masked=0 |
Directory | /workspace/9.kmac_test_vectors_shake_256/latest |
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